XC4062XLA

Features: XC4000XLA/XV Family FeaturesNote: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the same features as XLA devices, incorporate additional interconnect resources and extend gate capacity to 500,000 system gates. The XC4000XV devices require a separa...

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SeekIC No. : 004547867 Detail

XC4062XLA: Features: XC4000XLA/XV Family FeaturesNote: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the same features as XLA devices, incorporate additional interconne...

floor Price/Ceiling Price

Part Number:
XC4062XLA
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/13

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Product Details

Description



Features:

XC4000XLA/XV Family Features
Note: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the same features as XLA devices, incorporate additional interconnect resources and extend gate capacity to 500,000 system gates. The XC4000XV devices require a separate 2.5V power supply for internal logic but maintain 5V I/O compatibility via a separate 3.3V I/O power supply. For additional information about the XC4000XLA/XV device architecture, refer to the XC4000E/X FPGA Series general and functional descriptions.
• System-featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- Synchronous write option
- Dual-port RAM option
- Flexible function generators and abundant flip-flops
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• Flexible Array Architecture
• Low-power Segmented Routing Architecture
• Systems-oriented Features
- IEEE 1149.1-compatible boundary scan
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- Unlimited reprogrammability
• Read Back Capability
- Program verification and internal node observability

Electrical Features
• XLA Devices Require 3.0 - 3.6 V (VCC)
• XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)
• 5.0 V TTL compatible I/O
• 3.3 V LVTTL, LVCMOS compliant I/O
• 5.0 V and 3.0 V PCI Compliant I/O
• 12 mA or 24 mA Current Sink Capability
• Safe under All Power-up Sequences
• XLA Consumes 40% Less Power than XL
• XV Consumes 65% Less Power than XL
• Optional Input Clamping to VCC (XLA) or VCCIO (XV)

Additional Features
• Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power
• Advanced Technology - 5 layer metal, 0.25 mm CMOS
process (XV) or 0.35 mm CMOS process (XLA)
• Highest Performance - System erformance beyond
100 MHz
• High Capacity - Up to 500,000 system gates and
270,000 synchronous SRAM bits
• Low Power - 3.3 V/2.5 V technology plus segmented
routing architecture
• Safe and Easy to Use - Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices



Specifications

 
Maximum I/O Accessible per Package
Device Max
I/O
HQ160 PQ160 HQ208 PQ208 HQ240 PQ240 BG256 HQ304 BG352 BG432 PG559 BG560
XC4013XLA 192   129   160   192 192          
XC4020XLA 224   129   160   193 205          
XC4028XLA 256 129   160   193   205   256      
XC40250XV 288 129   160   193       289 288    
XC4044XLA 320 129   160   193     256 289 320    
XC4052XLA 352 129   160   193     256 289 352    
XC4062XLA 384 129   160   193     256 289 352   352
XC4085XLA 448 129   160   193     256 289 352   384
XC40110XV 448         178       274 336   448
XC40150XV 448         178       274 336 448 432
XC40200XV 448                   336   432
XC40250XV 448                   336 448 432



Description

XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays XC4062XLA (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array.

The result of fifteen years of FPGA XC4062XLA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs.


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