Features: • Third Generation Field-Programmable Gate Arrays
Abundant flip-flops
Flexible function generators
On-chip ultra-fast RAM
Dedicated high-speed carry-propagation circuit
Wide edge decoders (four per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution network
• Flexible Array Architecture
Programmable logic blocks and I/O blocks
Programmable interconnects and wide decoders
• Sub-micron CMOS Process
High-speed logic and Interconnect
Low power consumption
• Systems-Oriented Features
IEEE 1149.1-compatible boundary-scan logic support
Programmable output slew rate (2 modes)
Programmable input pull-up or pull-down resistors
12-mA sink current per output
24-mA sink current per output pair
• Configured by Loading Binary File
Unlimited reprogrammability
Six programming modes
• XACT Development System runs on '386/'486-type PC, NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 series
Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD
Fully automatic partitioning, placement and routing
Interactive design editor for design optimization
288 macros, 34 hard macros, RAM/ROM compiler
Specifications
|
SYMBOL |
Description |
RATINGS |
UNITS |
|
VCC |
Supply voltage relative to GND |
0.5 to +7.0 |
V |
|
VIN |
Input voltage with respect to GND |
0.5 to VCC +0.5 |
V |
|
VTS |
Voltage applied to 3-state output |
0.5 to VCC +0.5 |
V |
|
TSTG |
Storage temperature (ambient) |
65 to + 150 |
|
|
TSOL |
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) |
+ 260 |
|
|
TJ |
Junction temperature |
+ 150 |
|
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
DescriptionThe XC4000 family of Field-Programmable Gate Arrays (FPGAs) provides the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay, and inherent risk of a conventional masked gate array.
The XC4000 family provides a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs).
XC4000 devices have generous routing resources to accommodate the most complex interconnect patterns. They are customized by loading configuration data into the internal memory cells. The FPGA can either actively read its configuration data out of external serial or byte-parallel PROM (master modes), or the configuration data can be written into the FPGA (slave and peripheral modes).
The XC4000 family is supported by powerful and sophisticated software, covering every aspect of design: from schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation of the configuration bit stream.
Since Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hardware must be adapted to different user applications. FPGAs are ideal for shortening the design and development cycle, but they also offer a cost-effective solution for production rates well beyond 1000 systems per month.
For a detailed description of the device features, architecture, configuration methods and pin descriptions, see pages 2-9 through 2-45.
XC4000 Data Sheet
