XC4000E

The XC4000E family of Field-Programmable Gate Arrays (FPGAs) provides the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay, and inherent risk of a conventional masked gate array.
The  XC4000E family provides a regular, flexible,  programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs).
XC4000E devices have generous routing resources to accommodate the most complex interconnect patterns. They  are customized by loading configuration data into the internal memory cells. The FPGA can either actively read its configuration data out of external serial or byteparallel PROM (master modes), or the configuration data can be written into the FPGA (slave and peripheral modes).
The XC4000E family is supported by powerful and sophisticated software, covering every aspect of design: from schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation of the configuration bit stream.
FPGAs are  ideal for shortening the design and development cycle, but they also offer a cost-effective solution for production rates well beyond 1,000 systems per month.
The XC4000E family is a superset of the popular XC4000 family. For a detailed description of the device architecture, configuration methods, pin functionality, package pin-outs and dimensions, see the Xilinx Programmable Logic Data Book.
The following pages describes the new features of the XC4000E family and list electrical and timing parameters.