XC4013E-3BG240C

Features:

• Third Generation Field-Programmable Gate Arrays
On-chip ultra-fast RAM with synchronous write option
Dual-port RAM option
Fully PCI compliant
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry-propagation circuit
Wide edge decoders (four per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
8 global low-skew clock or signal distribution network
• Flexible Array Architecture
Programmable logic blocks and I/O blocks
Programmable interconnects and wide decoders
• Sub-micron CMOS Process
High-speed logic and Interconnect
Low power consumption
• Systems-Oriented Features
IEEE 1149.1-compatible boundary-scan logic support
Programmable output slew rate (2 modes)
Programmable input pull-up or pull-down resistors
12-mA sink current per output
24-mA sink current per output pair
• Configured by Loading Binary File
Unlimited reprogrammability
Six programming modes
• XACT Development System runs on '386/'486/ Pentium-type PC, Apollo, Sun-4, and Hewlett-Packard 700 series
Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD
Fully automatic partitioning, placement and routing
Interactive design editor for design optimization
288 macros, 34 hard macros, RAM/ROM compiler


Description

The XC4000E family of Field-Programmable Gate Arrays (FPGAs) provides the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay, and inherent risk of a conventional masked gate array.

The XC4000E family provides a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs).

XC4000E devices have generous routing resources to accommodate the most complex interconnect patterns. They are customized by loading configuration data into the internal memory cells. The FPGA can either actively read its configuration data out of external serial or byteparallel PROM (master modes), or the configuration data can be written into the FPGA (slave and peripheral modes).

The XC4000E family is supported by powerful and sophisticated software, covering every aspect of design: from schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation of the configuration bit stream.

FPGAs are ideal for shortening the design and development cycle, but they also offer a cost-effective solution for production rates well beyond 1,000 systems per month.

The XC4000E family is a superset of the popular XC4000 family. For a detailed description of the device architecture, configuration methods, pin functionality, package pin-outs and dimensions, see the Xilinx Programmable Logic Data Book.

The following pages describes the new features of the XC4000E family and list electrical and timing parameters.