XC4000X

Features:

* Highest Performance - 3.3 V XC4000XL
* Highest Capacity - Over 180,000 Usable Gates
* 5 V tolerant I/Os on XC4000XL
* 0.35 m SRAM process for XC4000XL
* Additional Routing Over XC4000E
   - almost twice the routing capacity for high-density designs
* Buffered Interconnect for Maximum Speed Blocks TM
* Improved VersaRing I/O Interconnect for Better Fixed Pinout Flexibility
* 12 mA Sink Current Per XC4000X Output
* Flexible New High-Speed Clock Network
   - EightadditionalEarlyBuffersforshorterclockdelays
   - Virtually unlimited number of clock signals
* Optional Multiplexer or 2-input Function Generator on Device Outputs
* Four Additional Address Bits in Master Parallel Configuration Mode
* XC4000XV Family offers the highest density with 0.25 m 2.5 V technology


Description

XC4000 Series devices are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). They have generous routing resources to accommodate the most complex interconnect patterns.

The devices are customized by loading configuration data into internal memory cells. The FPGA can either actively read its configuration data from an external serial or byte-parallel PROM (master modes), or the configuration data can be written into the FPGA from an external device (slave and peripheral modes).

XC4000 Series FPGAs are supported by powerful and sophisticated software, covering every aspect of design from schematic or behavioral entry, floor planning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and readback of the configuration bit stream.

Because Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hard- ware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a coseffective solution for produc- tionrateswellbeyond5,000systemspermonth.Forlowest high-volume unit cost, a design can first be implemented in the XC4000E or XC4000X, then migrated to one of Xilinx' compatible HardWire mask-programmed devices.