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WV3EG265M64EFSU-D4

Features: ` Double-data-rate architecture` PC2700 and PC2100` Bi-directional data strobes (DQS)` Differential clock inputs (CK & CK#)` Programmable Read Latency 2, 2.5 (clock)` Programmable Burst Length (2,4,8)` Programmable Burst type (sequential & interleave)` Auto and self refresh, (8K/...

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SeekIC No. : 004546961 Detail

WV3EG265M64EFSU-D4: Features: ` Double-data-rate architecture` PC2700 and PC2100` Bi-directional data strobes (DQS)` Differential clock inputs (CK & CK#)` Programmable Read Latency 2, 2.5 (clock)` Programmable Burs...

WV3EG265M64EFSU-D4 Data Sheet

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Part Number:
WV3EG265M64EFSU-D4
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

` Double-data-rate architecture
` PC2700 and PC2100
` Bi-directional data strobes (DQS)
` Differential clock inputs (CK & CK#)
` Programmable Read Latency 2, 2.5 (clock)
` Programmable Burst Length (2,4,8)
` Programmable Burst type (sequential & interleave)
` Auto and self refresh, (8K/64ms refresh)
` Serial presence detect with EEPROM
` Power supply: VCC/VCCQ: 2.5V ± 0.2V
` Dual Rank
` 200 pin SO-DIMM package
` Package height options: D4: 31.75 mm (1.25")


Specifications

Parameter Symbol Value Units
Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.3 V
Voltage on VCC supply relative to VSS VCC -1.0 to 3.6 V
Voltage on VCCQ supply relative to VSS VCCQ -1.0 to 3.6 V
Storage Temperature TSTG -55 to +150
Operating Temperature TA 0 to +70
Power Dissipation PD 16 W
Short Circuit Current IOS 50 mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The WV3EG265M64EFSU-D4 is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The WV3EG265M64EFSU-D4 consists of sixteen 64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages mounted on a 200 pin substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the WV3EG265M64EFSU-D4 to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.




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