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WV3EG128M72EFSR

Features: · Double-data-rate architecture· DDR266 and DDR333• JEDEC design specifi cations· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2,5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & inter...

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SeekIC No. : 004546952 Detail

WV3EG128M72EFSR: Features: · Double-data-rate architecture· DDR266 and DDR333• JEDEC design specifi cations· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Laten...

WV3EG128M72EFSR Data Sheet

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Part Number:
WV3EG128M72EFSR
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Double-data-rate architecture
· DDR266 and DDR333
•  JEDEC design specifi cations
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2,5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input
· Auto and self refresh
· Serial presence detect
· Power Supply:
     • VCC = VCCQ = +2.5V ±0.2V (100, 133 and 166MHz)
· 184 pin DIMM package
· PCB height:
     • D3: 29.97mm (1.18")


Specifications

Symbol
Parameter
Rating
 Units
VIN, VOUT
Voltage on any pin relative to VSS
-0.5 to 3.3
V
VCC
Voltage on VCC supply relative to VSS
-1.0 to 3.6
V
VCCQ
Voltage on VCC supply relative to VSS
-1.0 to 3.6
V
TSTG
Storage Temperature
-55 to +150
°C
PD
Power Dissipation
18
W
IOS
Short Circuit Current
50
mA
Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
          Functional operation should be restricted to recommended operating condition.
          Exposure to higher than recommended voltage for extended periods of time could affect device reliability


Description

The WV3EG128M72EFSR is a 128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eighteen 64Mx8 DDR components in FBGA packages mounted on a 184 Pin FR4 substrate.
 
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

* This product is under development, is not qualifi ed or characterized and is subject to change or cancellation without notice.




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