Features: ·Package:
• 275 Plastic Ball Grid Array (PBGA), 32mm x 25mm
·Commercial, Industrial and Military Temperature Ranges
·Weight:
• WEDPNF8M722V-XBX - 2.5 grams typicalSpecifications
| Parameter |
|
Unit |
| Supply Voltage Range (VCC) |
-0.5 to +4.0 |
V |
| Signal Voltage Range |
-0.5 to Vcc +0.5 |
V |
| Operating Temperature TA (Mil) |
-55 to +125 |
|
| Operating Temperature TA (Ind) |
-40 to +85 |
|
| Storage Temperature, Plastic |
-65 to +150 |
|
| Flash Endurance (write/erase cycles) |
1,000,000 min. |
cycles |
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.DescriptionThe WEDPNF8M722V-XBX is a high-speed CMOS, dynamic random-access ,memory using 5 chips containing 134, 217, 728 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
Read and write accesses to the WEDPNF8M722V-XBX is burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The WEDPNF8M722V-XBX provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
The WEDPNF8M722V-XBX uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.
The WEDPNF8M722V-XBX is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode.
All inputs and outputs of WEDPNF8M722V-XBX are LVTTL compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
WEDPNF8M722V-XBX Data Sheet
