WEDPN4M64V-XBX

The WEDPN4M64V-XBX is a high-speed CMOS, dynamic random-access ,memory using 4 chips ontaining ,108,864 bits. Each chip is internally con gured as a quad-bank DRAM with a synchronous interface. Each of the chips 6,777,216-bit banks is organized as 4,096 rows by256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a med number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which en followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used lect the bank and row to be accessed (BA0, BA1 select the bank; A0-11 select the row). The address bits registered ncident with the READ or WRITE command are used to select the starting column location for the burst access.

The WEDPN4M64V-XBX provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a rst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated t the end of the burst sequence.

The WEDPN4M64V-XBX uses an internal pipelined architecture to achieve high-speed operation. This architecture is mpatible with the 2n rule of prefetch architectures, but WEDPN4M64V-XBX also allows the column address to be changed on every clock cycle to e a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the rge cycles and provide seamless, high-speed, random-access operation.

The WEDPN4M64V-XBX is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, long a power-saving, power-down mode.