Features: ·High Frequency = 100, 125, 133MHz
·Package:
219 Plastic Ball Grid Array (PBGA), 21 x 21mm
·Single 3.3V 0.3V power suppl
·Fully Synchronous; all signals registered on positive
edge of system clock cycle
·Internal pipelined operation; column address can be
changed every clock cycle
·Internal banks for hiding row access/precharge
·Programmable Burst length 1,2,4,8 or full page
·4096 refresh cycles
·Commercial, Industrial and Military Temperature
Ranges
·Organized as 4M x 64
User Con gurable as 2x4Mx32 or 4x4Mx16
·Weight: WEDPN4M64V-XBX - 2 grams typicalSpecifications
| Parameter |
|
Unit |
| Voltage on VCC Supply relative to Vss |
-1 to 4.6 |
V |
| Voltage on NC or I/O pins relative to Vss |
-1 to 4.6 |
V |
| Operating Temperature TA (Mil) |
-55 to +125 |
|
| Operating Temperature TA (Ind) |
-40 to +85 |
|
| Storage Temperature, Plastic |
-55 to +125 |
|
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanen
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions greater than those indicated in the operational sections
of this speci cation is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.DescriptionThe WEDPN4M64V-XBX is a high-speed CMOS, dynamic random-access ,memory using 4 chips ontaining ,108,864 bits. Each chip is internally con gured as a quad-bank DRAM with a synchronous interface. Each of the chips 6,777,216-bit banks is organized as 4,096 rows by256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a med number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which en followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used lect the bank and row to be accessed (BA0, BA1 select the bank; A0-11 select the row). The address bits registered ncident with the READ or WRITE command are used to select the starting column location for the burst access.
The WEDPN4M64V-XBX provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a rst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated t the end of the burst sequence.
The WEDPN4M64V-XBX uses an internal pipelined architecture to achieve high-speed operation. This architecture is mpatible with the 2n rule of prefetch architectures, but WEDPN4M64V-XBX also allows the column address to be changed on every clock cycle to e a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the rge cycles and provide seamless, high-speed, random-access operation.
The WEDPN4M64V-XBX is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, long a power-saving, power-down mode.
WEDPN4M64V-XBX Data Sheet
