Features: ·3.3 /3.3 +/- 10% power supply·524,288 words x 2 banks x 16 bits organization·CAS latency: 2 and 3·Burst Length: 1, 2, 4, 8, and full page·Burst read, Single Write Mode·Byte data controlled by UDQM and LDQM·Auto-precharge and controlled precharge·4K refresh cycles/64 mS·Interface: LVTTL·...
W9816G6CH: Features: ·3.3 /3.3 +/- 10% power supply·524,288 words x 2 banks x 16 bits organization·CAS latency: 2 and 3·Burst Length: 1, 2, 4, 8, and full page·Burst read, Single Write Mode·Byte data controlle...
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PARAMETER |
SYMBOL |
RATING |
UNIT |
NOTES |
Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current |
VIN, VOUT VCC, VCCQ TOPR TSTG TSOLDER PD IOUT |
-1 − VCC+0.3 -1 − 4.6 0 − 70 -55 − 150 260 1 50 |
V V W mA |
1 1 1 1 1 1 1 |
W9816G6CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 2 banks × 16 bits. Using pipelined architecture and 0.13 µm process technology, W9816G6CH delivers a data bandwidth of up to 400M bytes per second (-5). For different applications the W9816G6CH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200Mhz/CL3. The -6 parts can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3. For handheld device application.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing W9816G6CH's address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9816G6CH is ideal for main memory in high performance applications.