W981208AH

W981208AH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 4M words x 4 banks x 8 bits. Using pipelined architecture and 0.20um process technology, W981208AH delivers a data bandwidth of up to 133M ( - 75) bytes per second. To fully comply to the personal computer industrial standard, W981208AH is sorted into two speed grades: -75 and -8H. The -75 is compliant to the PC133 specitication, The -8H is compliant to the PC100/CL2 specification.

Accesses to the SDRAM W981208AH are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM W981208AH internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981208AH is ideal for main memory in high performance applications.