W981208BH

W981208BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 4M words ×4 banks × 8 bits. Using pipelined architecture and 0.175 mm process technology, W981208BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the personal computer industrial standard, W981208BH is sorted into three speed grades: -7, -75 and - 8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981208BH is ideal for main memory in high performance applications.