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V58C3643204SAT

Features: 4 banks x 512K x 32 organizationHigh speed data transfer rates with system frequency up to 225 MHzData Mask for Write Control (DM)Four Banks controlled by BA0 & BA1Programmable CAS Latency: 3, 4Programmable Wrap Sequence: Sequential or InterleaveProgrammable Burst Length: 2, 4, 8 ful...

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SeekIC No. : 004540078 Detail

V58C3643204SAT: Features: 4 banks x 512K x 32 organizationHigh speed data transfer rates with system frequency up to 225 MHzData Mask for Write Control (DM)Four Banks controlled by BA0 & BA1Programmable CAS Lat...

V58C3643204SAT Data Sheet

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Part Number:
V58C3643204SAT
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

 4 banks x 512K x 32 organization
 High speed data transfer rates with system frequency up to 225 MHz
 Data Mask for Write Control (DM)
 Four Banks controlled by BA0 & BA1
 Programmable CAS Latency: 3, 4
 Programmable Wrap Sequence: Sequential or Interleave
 Programmable Burst Length:
    2, 4, 8 full page for Sequential Type
    2, 4, 8 full page for Interleave Type
 Automatic and Controlled Precharge Command
 Suspend Mode and Power Down Mode
 Auto Refresh and Self Refresh
 Refresh Interval: 2048 cycles/16ms
 Available in 100-pin TQFP
 SSTL-2 Compatible I/Os
 Double Data Rate (DDR)
 Bidirectional Data Strobe (DQs) for input and output data, active on both edges
 On-Chip DLL aligns DQ and DQs transitions with CLK transitions
 Differential clock inputs CLK and CLK
 Power Supply 3.3V ± 0.3V


Pinout

Connection Diagram


Specifications

Parameter
Symbol
Commercial
Units
Voltage on any pin relative to VSS

VIN, VOUT

-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS

VDD, VDDQ
-1.0 ~ 4.6
V
Storage temperature

TSTG

-55 ~ +150
°C
Power dissipation

PD

1.6
W

Short circuit current

IOS

50

mA




Description

The V58C3643204SAT is a four bank DDR RAM organized as 4 banks x 512K x 32. The V58C3643204SAT achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.




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