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V58C2128(804/404/164)S

Features: High speed data transfer rates with system frequency up to 166 MHz Data Mask for Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 2.5 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for ...

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SeekIC No. : 004540073 Detail

V58C2128(804/404/164)S: Features: High speed data transfer rates with system frequency up to 166 MHz Data Mask for Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 2.5 Programmable Wrap Se...

V58C2128(804/404/164)S Data Sheet

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Part Number:
V58C2128(804/404/164)S
Supply Ability:
5000

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Product Details

Description



Features:

High speed data transfer rates with system frequency up to 166 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length:
    2, 4, 8 for Sequential Type
    2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 66-pin 400 mil TSOP
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
QFC options for FET control. x4 parts.


Pinout

Connection Diagram


Specifications

Operating temperature range ...................................................................0 to 70 °C
Storage temperature range .................................................................-55 to 150 °C
VDDSupply Voltage Relative to VSS.........................................................-1V to +3.6V
VDDQ Supply Voltage Relative to VSS.....................................................-1V to +3.6V
VREF and Inputs Voltage Relative to VSS................................................-1V to +3.6V
I/O Pins Voltage Relative to VSS................................................. -0.5V to VDDQ+0.5V
Power dissipation ............................................................................................ 1.6 W
Data out current (short circuit) ........................................................................ 50 mA


Description

The V58C2128(804/404/164)S is a four bank DDR DRAM organized as 4 banks x 4Mbit x 8 (804), 4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4 (164). The V58C2128(804/404/164)S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.

All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are ocurring on both edges of DQS.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.




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