V43644R04V(C)TG-10PC

Features: 168 Pin Unbuffered 4,194,304 x 64 bit Oganization SDRAM ModulesUtilizes High Performance 4M x 16 SDRAM in TSOPII-54 PackagesFully PC Board Layout Compatible to INTEL'S Rev 1.0 Module SpecificationSingle +3.3V (± 0.3V) Power SupplyProgrammableCAS Latency, Burst Length, and Wrap Sequence (...

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SeekIC No. : 004539819 Detail

V43644R04V(C)TG-10PC: Features: 168 Pin Unbuffered 4,194,304 x 64 bit Oganization SDRAM ModulesUtilizes High Performance 4M x 16 SDRAM in TSOPII-54 PackagesFully PC Board Layout Compatible to INTEL'S Rev 1.0 Module Speci...

floor Price/Ceiling Price

Part Number:
V43644R04V(C)TG-10PC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

 168 Pin Unbuffered 4,194,304 x 64 bit Oganization SDRAM Modules
 Utilizes High Performance 4M x 16 SDRAM in TSOPII-54 Packages
 Fully PC Board Layout Compatible to INTEL'S Rev 1.0 Module Specification
 Single +3.3V (± 0.3V) Power Supply
 Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
 Auto Refresh (CBR) and Self Refresh
 All Inputs, Outputs are LVTTL Compatible
 4096 Refresh Cycles every 64 ms
 Serial Present Detect (SPD)
 SDRAM Performance



Specifications

Symbol

Parameter

Limit Values

Unit

Min.

Max.

VIH

Input High Voltage

2.0

VCC+0.3

V

VIL

Input Low Voltage

0.5

0.8

V

VOH

Output High Voltage (IOUT = 2.0 mA)

2.4

-

V

VOL

Output Low Voltage (IOUT = 2.0 mA)

-

0.4

V

II(L)

Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)

40

40

mA

IO(L)

Output leakage current
(DQ is disabled, 0V < VOUT < VCC)

40

40

mA




Description

The V43644R04V(C)TG-10PC memory module is organized 4,194,304 x 64 bits in a 168 pin dual in line memory module (DIMM). The 4M x 64 memory module uses 4 Mosel-Vitelic 4M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.




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