V436416S04V(C)TG-10PC Selling Leads, Price trend, V436416S04V(C)TG-10PC DataSheet download, circuit diagram from SeekIC.com

Features: 168 Pin Unbuffered 16,777,216 x 64 bit Oganization SDRAM ModulesUtilizes High Performance 8M x 8 SDRAM in TSOPII-54 PackagesFully PC Board Layout Compatible to INTEL'S Rev 1.0 Module SpecificationSingle +3.3V (± 0.3V) Power SupplyProgrammableCAS Latency, Burst Length, and Wrap Sequence (...

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SeekIC No. : 004539817 Detail

V436416S04V(C)TG-10PC: Features: 168 Pin Unbuffered 16,777,216 x 64 bit Oganization SDRAM ModulesUtilizes High Performance 8M x 8 SDRAM in TSOPII-54 PackagesFully PC Board Layout Compatible to INTEL'S Rev 1.0 Module Speci...

V436416S04V(C)TG-10PC Data Sheet

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Part Number:: V436416S04V(C)TG-10PC
Supply Ability:: 5000

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1~5000

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Upload time: 2024/12/21

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Product Details

Description

Features:

168 Pin Unbuffered 16,777,216 x 64 bit Oganization SDRAM Modules
Utilizes High Performance 8M x 8 SDRAM in TSOPII-54 Packages
Fully PC Board Layout Compatible to INTEL'S Rev 1.0 Module Specification
Single +3.3V (± 0.3V) Power Supply
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are LVTTL Compatible
4096 Refresh Cycles every 64 ms
Serial Present Detect (SPD)
SDRAM Performance

Specifications

Symbol	Parameter	Limit Values		Unit
Symbol	Parameter	Min.	Max.	Unit
V_IH	Input High Voltage	2.0	V_CC+0.3	V
V_IL	Input Low Voltage	0.5	0.8	V
V_OH	Output High Voltage (I_OUT= 2.0 mA)	2.4	-	V
V_OL	Output Low Voltage (I_OUT = 2.0 mA)	-	0.4	V
I_I(L)	Input Leakage Current, any input (0 V < V_IN < 3.6 V, all other inputs = 0V)	40	40	mA
I_O(L)	Output leakage current (DQ is disabled, 0V < V_OUT< V_CC)	40	40	mA

Description

The V436416S04V(C)TG-10PC memory module is organized 16,777,216 x 64 bits in a 168 pin dual in line memory module (DIMM). The 16M x 64 unbuffered DIMM uses 16 Mosel-Vitelic 8M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.

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