Features: · Complete MIL-STD-1553B remote terminal interface· 1K x 16 of on-chip static RAM for message data, completely accessible to host· Self-test capability, including continuous loop-back compare· Programmable memory mapping via pointers for efficient use of internal memory, including buffer...
UT1553B RTR: Features: · Complete MIL-STD-1553B remote terminal interface· 1K x 16 of on-chip static RAM for message data, completely accessible to host· Self-test capability, including continuous loop-back comp...
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Features: Comprehensive MIL-STD-1553 dual-redundant Bus Controller (BC) and Remote Terminal (RT) ...
Features: `Complete MIL-STD-1553B Remote Terminalerface compliance`Dual-redundant data bus operati...
SYMBOL | PARAMETER |
LIMITS |
UNIT |
VDD | DC supply voltage |
-0.3 to +7.0 |
V |
VIO | Voltage on any pin |
-0.3 to VDD+0.3 |
V |
II | DC input current |
±10 |
mA |
TSTG | Storage temperature |
-65 to +150 |
°C |
PD | Maximum power dissipation |
300 |
mW |
TJ | Maximum junction temperature |
+175 |
°C |
QJC | Thermal resistance, junction-to-case |
20 |
°C/W |
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The UT1553B RTR is a monolithic CMOS VLSI solution to the requirements of the dual-redundant MIL-STD-1553B interface. Designed to reduce cost and space, the RTR integrates the remote terminal logic with a user-configured 1K x 16 static RAM. In addition, the RTR has a flexible subsystem interface to permit use with most processors or controllers.
The UT1553B RTR provides all protocol, data handling, error checking, and memory control functions, as well as comprehensive self-test capabilities. The UT1553B RTR's memory meets all of MIL-STD-1553B message storage needs through user-defined memory mapping. This memorymapped architecture allows multiple message buffering at.