Features: SpecificationsDescriptionThe USC1841 has the following features including Four 8 bit voltage output DACs;Microprocessor peripheral;TTL/CMOS compatible;Single (5-15V) supply;3us settling time (typical). The USC1841 contains four8 bit Digital to Analog Converters (DACj, with output amplif...
USC1841: Features: SpecificationsDescriptionThe USC1841 has the following features including Four 8 bit voltage output DACs;Microprocessor peripheral;TTL/CMOS compatible;Single (5-15V) supply;3us settling ti...
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DescriptionThe USC1841-BI-P20 is designed as one kind of universal semiconductors which contains f...
The USC1841 has the following features including Four 8 bit voltage output DACs;Microprocessor peripheral;TTL/CMOS compatible;Single (5-15V) supply;3us settling time (typical).
The USC1841 contains four8 bit Digital to Analog Converters (DACj, with output amplifiers and digital interface logic and storage for each DAC. Full specified performance is achieved without trim. "Fhe chip contains 8 bit latches for each of the four DACs. Data transfer is over a common 8 bit bus into the four ports/latches. Lines AO and A1 determine which port is loaded when WR* goes low. Each DAC has an output buffer capable of driving SmA. Performance is guaranteed for input reference voltages from 2 to 12V. The USC1841 has been designed to operate with a single power supply. The USC1841 is a functional replacement for Analog Devices part number AD7226.Selection of the desired DAC is controlled by address lines AO and A1 as shown by the truth table (Table 1). Data from the 8 bit wide input port will be transferred to the latches of the selected port while WR* is low. Changes on the data bus during the low period of WR* will be reflected on the output. Data is latched on the rising edge of the WR*.
The four DACs each contain a 256-step resistive ladder made up of poly resistors with a nominal 100 ohm resistance per seep.This provides a full monotonic range fram VHF to AGNp. The appropriate tap of the ladder is sclccted through a 1/256 decoder by the latched digital information. The load on the reference is not switched, hence the reference load impedance will not change with the code. The load will be the parallel combination of the four ladders.The tapped voltage from the reference string selected by the decoder is placed into a unity gain non-inverting CMOS buffer amplifier. This produces a digitally programmed voltage source where Voarr (A-D)=DL (A-D) x V}r. DL (A-D) is the digital latched data for the appropriate channels. The USC1841 has been designed to drive atleast 5mA into a 2K load.A slew enhancement circuit has been added to assist in changing the output to its new level quickly. This means that the output will slew very rapidly toward the selected value and then settle into the final value without overshoot.