Features: 1.1 General` 2.7 to 3.6 V power supply` Integrated digital filter and Digital-to-Analog Converter (DAC)` 256fs system clock output` 20-bit data path in interpolator` High performance` No analog post filtering required for DAC` Supporting sampling frequencies from 28 up to 55 kHz.1.2 Cont...
UDA1352TS: Features: 1.1 General` 2.7 to 3.6 V power supply` Integrated digital filter and Digital-to-Analog Converter (DAC)` 256fs system clock output` 20-bit data path in interpolator` High performance` No a...
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Features: 1.1 General· Low power consumption.· 2.7 to 3.6 V power supply.· Selectable control via ...
1.1 General
` 2.7 to 3.6 V power supply
` Integrated digital filter and Digital-to-Analog Converter (DAC)
` 256fs system clock output
` 20-bit data path in interpolator
` High performance
` No analog post filtering required for DAC
` Supporting sampling frequencies from 28 up to 55 kHz.
1.2 Control
` Controlled either by means of static pins, I2C-bus or L3-bus microcontroller interface.
1.3 IEC 60958 input
` On-chip amplifier for converting IEC 60958 input to CMOS levels
` Lock indication signal available on pin LOCK
` Information of the Pulse Code Modulation (PCM) status bit and the non-PCM data detection is available on pin PCMDET
` For left and right 40 key channel-status bits available via L3-bus or I2C-bus interface.
1.4 Digital sound processing and DAC
` Automatic de-emphasis when using IEC 60958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies
` Soft mute by means of a cosine roll-off circuit selectable via pin MUTE, L3-bus or I2C-bus interface
` Left and right independent dB linear volume control with 0.25 dB steps from 0 to -50 dB, 1 dB steps to -60,-66 and - dB
` Bass boost and treble control in L3-bus or I2C-bus mode
` Interpolating filter (fs to 64fs) by means of a cascade of a recursive filter and a FIR filter
` Fifth-order noise shaper (operating at 64fs) generates the bitstream for the DAC
` Filter Stream DAC (FSDAC).
SYMBOL | PARAMETER | CONDITIONS | MIN. | MAX. |
UNIT |
VDD | supply voltage | note 1 | 2.7 | 5.0 |
V |
Tstg | storage temperature | -65 | +125 | ||
Tamb | ambient temperature | -40 | +85 | ||
Vesd | electrostatic discharge voltage | Human Body Model (HBM); note 2 | -2000 | +2000 |
V |
Machine Model (MM); note 3 | -200 | +200 |
V | ||
Ilu(prot) | latch-up protection current | Tamb = 125 °C; VDD = 3.6 V | - | 200 |
mA |
Isc(DAC) | short-circuit current of DAC | Tamb = 0 °C; VDD = 3 V; note 4 output short-circuited to VSSA(DAC) output short-circuited to VDDA(DAC) |
- - |
20 100 |
mA mA |
The UDA1352TS is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques.
A lock indication signal is available on pin LOCK, indicating that the IEC 60958 decoder is locked. A separate pin PCMDET is available to indicate whether or not the PCM data is applied to the input.
By default, the DAC output is muted when the decoder is out-of-lock. However, this setting can be overruled in the L3-bus or I2C-bus mode.
The UDA1352TS has IEC 60958 input to the DAC only and is in SSOP28 package.
Besides the UDA1352TS, the UDA1352HL is also available. The UDA1352HL is the full featured version in LQFP48 package.