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UDA1351H

Features: 1.1 General` 2.7 to 3.6 V power supply` Integrated digital filter and Digital-to-Analog Converter (DAC)` Master-mode data output interface for off-chip sound processing` 256fs system clock output` 20-bit data-path in interpolator` High performance` No analog post filtering required for D...

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UDA1351H: Features: 1.1 General` 2.7 to 3.6 V power supply` Integrated digital filter and Digital-to-Analog Converter (DAC)` Master-mode data output interface for off-chip sound processing` 256fs system clock...

UDA1351H Data Sheet

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Part Number:
UDA1351H
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
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  • 15 Days
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Product Details

Description



Features:

1.1 General
` 2.7 to 3.6 V power supply
` Integrated digital filter and Digital-to-Analog Converter (DAC)
` Master-mode data output interface for off-chip sound processing
` 256fs system clock output
` 20-bit data-path in interpolator
` High performance
` No analog post filtering required for DAC
` Supports sampling frequencies from 28 up to 100 kHz
` The UDA1351H is fully pin and function compatible with the UDA1350AH.
1.2 Control
` Controlled either by means of static pins or via the L3 microcontroller interface.
1.3 IEC 958 input
` On-chip amplifier for converting IEC 958 input to CMOS
levels
` Selectable IEC 958 input channel, one out of two
` Lock indication signal available on pin LOCK
` Lock indication signal combined on-chip with the Pulse Code Modulation (PCM) status bit; in case non-PCM has been detected pin LOCK indicates out-of-lock
` Key channel-status bits available via L3 interface (lock, pre-emphasis, audio sample frequency, 2 channel PCM indication and clock accuracy).
1.4 Digital output and input interfaces
` When the UDA1351H is clock master of the data output interfaces:
   BCKO and WSO signals are output
   I2S-bus or LSB-justified 16, 20 and 24 bits formats are supported.
` When the UDA1351H is clock slave of the data input interface:
   BCK and WS signals are input
   I2S-bus or LSB-justified 16, 20 and 24 bits formats are supported.
1.5 Digital sound processing and DAC
` Pre-emphasis information of IEC 958 input bitstream available in L3 interface register and on pins
` Automatic de-emphasis when using IEC 958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies
` Soft mute by means of a cosine roll-off circuit selectable via pin MUTE or the L3 interface
` Interpolating filter (fs to 128fs) by means of a cascade of a recursive filter and a FIR filter
` Third-order noise shaper operating at 128fs generates bitstream for the DAC
` Filter stream digital-to-analog converter


Application

· Digital audio systems.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX.
UNIT
VDD supply voltage note 1 2.7 5.0
V
Txtal crystal temperature   -25 +150
Tstg storage temperature   -65 +125
Tamb ambient temperature   -40 +85
Vesd electrostatic discharge voltage Human Body Model (HBM); note 2 -2000 +2000
V
Machine Model (MM) -200 +200
V
Ilu(prot) latch-up protection current note 3 - 200
mA
Isc(DAC) short-circuit current of DAC note 4
output short-circuited to VSSA(DAC)
output short-circuited to VDDA(DAC)		 -
-		 482
346
mA
mA

1. All VDD and VSS connections must be made to the same power supply.
2. JEDEC class 2 compliant, except pin VSSA(PLL) which can withstand ESD pulses of -1600 to +1600 V.
3. Latch-up test at Tamb = 125 °C and VDD = 3.6 V.
4. Short-circuit test at Tamb = 0 °C and VDD = 3 V. DAC operation after short-circuiting cannot be warranted.



Description

The UDA1351H is a single chip IEC 958 audio decoder with an integrated stereo digital-to-analog converter employing bitstream conversion techniques.

Besides the UDA1351H, which is the full featured version  in QFP44 package, there also exists the UDA1351TS.  The UDA1351TS has IEC 958 input to the DAC only and is in SSOP28 package.

The UDA1351H can operate in various operating modes:
· IEC 958 input to the DAC including on-chip signal processing
· IEC 958 input via the digital data output interface to the external Digital Signal Processor (DSP)
· IEC 958 input to the DAC and a DSP
· IEC 958 input via a DSP to the DAC including on-chip signal processing
· External source data input to the DAC including on-chip signal processing

The IEC 958 input audio data including the accompanying pre-emphasis information is available on the output data interface.

A lock indication signal is available on pin LOCK indicating that the IEC 958 decoder is locked.

By default the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode.




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