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UDA1350ATS

Features: 1 FEATURES1.1 General` 2.7 to 3.6 V power supply` Integrated digital filter and Digital-to-Analog Converter (DAC)` 256fs system clock output` 20-bit data path in interpolator` High performance` No analog post filtering required for DAC.1.2 Control` Controlled either by means of static pi...

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UDA1350ATS: Features: 1 FEATURES1.1 General` 2.7 to 3.6 V power supply` Integrated digital filter and Digital-to-Analog Converter (DAC)` 256fs system clock output` 20-bit data path in interpolator` High perform...

UDA1350ATS Data Sheet

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Part Number:
UDA1350ATS
Supply Ability:
5000

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Product Details

Description



Features:

1 FEATURES
1.1 General
` 2.7 to 3.6 V power supply
` Integrated digital filter and Digital-to-Analog Converter (DAC)
` 256fs system clock output
` 20-bit data path in interpolator
` High performance
` No analog post filtering required for DAC.
1.2 Control
` Controlled either by means of static pins or via the L3 microcontroller interface.
1.3 IEC 958 input
` On-chip amplifier for converting IEC 958 input to CMOS levels
` Lock indication signal available on pin LOCK
` Lock indication signal combined on-chip with the Pulse
    Code Modulation (PCM) status bit; in case non-PCM has been detected pin LOCK indicates out-of-lock
` Key channel-status bits available via L3 interface (lock,pre-emphasis, audio sample frequency, two channel PCM indication and clock accuracy).
1.4 Digital sound processing and DAC
` Automatic de-emphasis when using IEC 958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies
` Soft mute by means of a cosine roll-off circuit selectable via pin MUTE or the L3 interface
` dB linear volume control with 1 dB steps from 0 dB to -60 dB and - dB
` Bass boost and treble control in L3 control mode
` Interpolating filter (fs to 128fs) by means of a cascade of a recursive filter and a FIR filter
` Third order noise shaper operating at 128fs generates the bitstream for the DAC
` Filter stream digital-to-analog converter.



Application

· Digital audio systems.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX.
UNIT
VDD supply voltage                                                    note 1 2.7 5.0
V
Txtal crystal temperature -25 +150
Tstg storage temperature -65 +125
Tamb ambient temperature -40 +85
Vesd electrostatic discharge voltage Human Body Model (HBM);         note 2 -2000 +2000
V
Machine Model (MM)                   note 3 -200 +200
V
Ilu(prot) latch-up protection current Tamb = 125 °C; VDD = 3.6 V - 200
mA
Isc(DAC) short-circuit current of DAC Tamb = 0 °C; VDD = 3 V;          note 4
output short-circuited to VSSA(DAC)
output short-circuited to VDDA(DAC)		 -
-		 482
346
mA
mA

1. All VDD and VSS connections must be made to the same power supply.
2. JEDEC class 2 compliant.
3.JEDEC class B compliant, except pin VSSA(PLL) which can withstand ESD pulses of -130 to +130 V.
4.DAC operation after short-circuiting cannot be warranted.


Description

Available in two versions:
` UDA1350ATS:
   only IEC 958 input to DAC in SSOP28 package.
` UDA1350AH:
   full featured version in QFP44 package.

The UDA1350ATS is a single chip IEC 958 audio decoder with an integrated stereo digital-to-analog converter employing bitstream conversion techniques.

A lock indication signal is available on pin LOCK indicating that the IEC 958 decoder is locked. This pin is also used to indicate whether PCM data is applied to the input or not. In the event non-PCM data has been detected, the device indicates out-of-lock.

By default the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode.




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