U6224B-AFP

The U6224B-AFP has the following features including Low power consumption (typ. 5 V/35 mA);Eleclroslatic protection according to MIL-STD 883;SO-16 small package;1.3 GHz divide-by-8 prescaler integrated (can be bridged);EASY LINK INTERFACE to MOSMIC and MIXER-IC.

The U6224B is programmed via 2-wirc I2C-bus or 3-wire-bus depending on the received data format. The three bus inputs pin 4, 5, 10 are used as SDA, SCL and address select inputs in I2C-bus mode or as data, clock and enable inputs in 3-wire-bus mode. The data includes the scaling factor SF and switching output information. In I2C-bus mode there ai-e some additional functions available (ADC, bidirectional poets, etc.).The input amplifier together with a divide-by-8 prescaler gives an excellent sensitivity (see `TYPICAL PRES-CALER INPUT SENSITIVITY'). The input impedance is shown in the diagram `TYPICAL INPUT IM-PEDANCE'. When a new divider ratio according to the requested fVCO is entered, the phase detector and charge pump together with the tuning amplifier adjusts the control voltage of the VCO until the output signals of the programmable divider and the reference divider are in frequency and phase locked. The reference frequency may be provided by an external source capacitively coupled into pin 2, or by using an on-board crystal with an 18 pF capacitor in series.

The control byte CB2 programs U6224B-AFP the port outputs PO-2 and P6; for the MOSMIC ports PO-2 a logic 1 for high impedance output (off) or a logic 0 for low impedance output and for the standard port P6 a logic 0 for high impedance output (off) or a logic 1 for low impedance output (on). At power-on the MOSMIC pods PO-2 are sel to low impedance dale and the standard port P6 to high impedance stale.The OS-bit function disables the complete PLL function.U6224B-AFP allows the tuner alignment by supplying the tuning voltage directly through the 30 V supply voltage of the tuner.