U6223B

The U6223B has the following features including Only one device for 3-wire bus applications and I2C bus applications necessary (universal bus);High input frcqucncy of 2.9 GHz applicablc for all TV satellites;Low powcr consumption (typical 5 V/23 mA);Electrostatic protection according to MIL-STD 883.

The U6223B is programmed via a 2-wire I2C bus or 3-wire bus depending on the received data format. The three bus inputs pins 4, 5 and 10 are used as SDA, SCL and address select inputs in I2C bus mode and as data, clock and enable inputs in 3-wire bus mode. The data of U6223B includes the  scaling  factor  SF  (15-bit)  and  switching  output information. In I2C-bus mode, there are some additional functions for testing of the device included.The U6223B is function and pin equiralent to the U6225B apart from the switchable reference divider. A typical application  is  shown  on  page  12.  All  input/ output interface circuits are shown on page 9. Some special features  which  are  related  to  test-  and  alignment procedures for tuner production, ai-e explained together within the following bus mode description.The charge pump current can only be controlled in I2C bus mode. In 3-wire bus mode, there is always the high charge pump current active. The OS-bit function disables the  complete  PLL  function. This  enables  the  tuner alignment  by  supplying  the  tuning  voltage  directly through the 30 V supply voltage of the tuner.

When the U6225B-B is controlled via 3-wire bus format,then DATA, CLOCK and ENABLE signals are fed into the SDA,  SCL and AS/ENA fines respectively. The diagram `3-WIRE-BUS PULSE DIAGRAM,shows the dales formal. The dales consist of a single word, which contains   the   programmable   divider   and   switch information. The data is only clocked into the internal data shift register on the negative clock transition during the enable lung period on the negative clock transition.During enable low pcriods, the clock input of U6223B is disabled.New data words are only acccptcd by the intcrnal data latches from the shift register on a ncgativc transition of the enable signal if exactly ninctccn clock pulscs were sent during the high period. The data sequence and the timing is described in the following diagrams.