Features: SpecificationsDescriptionThe U6223B-AFP has the following features including 3-wire-bus mode:4 switching outputs(open collector),Locksignal output(open collector);Low power consumption (typical 5 V/23 mA);Electrostatic protection according to DAL-STD 883;2.9 GHz divide-by-16 prescaler in...
U6223B-AFP: Features: SpecificationsDescriptionThe U6223B-AFP has the following features including 3-wire-bus mode:4 switching outputs(open collector),Locksignal output(open collector);Low power consumption (ty...
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The U6223B-AFP has the following features including 3-wire-bus mode:4 switching outputs(open collector),Locksignal output(open collector);Low power consumption (typical 5 V/23 mA);Electrostatic protection according to DAL-STD 883;2.9 GHz divide-by-16 prescaler integrated.
The U6223B is programmed via 2-wire I2C bus or 3-wire bus depending on the received data format. The three bus inputs pins 4, 5 and 10 are used as SDA, SCL and address select inputs in hC-bus mode and as data, clock and enable inputs in 3-wire bus mode. The data includes the scaling factor SF (15 bit) and switching output informafion. In I2C-bus mode there are some additional functions foal testing of the device included.The U6223B is function and pin evivalent to the U6225B apart from the switchable reference divider. A typical application is shown on page?.All input / output interface circuits are shown on page?.Some special features which are related to test- and alignment procedures for tuner production are explained together within the following bus mode description.
When the U6223B is controlled via 2-wire I2C-bus format, then data and clock signals are fed into the SDA and SCL lines respectively. The table 'nC-BUS DATA FORMAT' describes the format of the data and shows how to select the device address by applying a voltage at pin 10. When the correct address byte is received, the SDA line is pulled low by the device during the acknowledge period, and then also during the acknowledge periods, when addifional data bytes are programmed.After the address transmission (first byte), data bytes can be sent to the device. There are four data bytes of U6223B-AFP requested to fully program the U6223B-AFP. The table 'hC-BUS PULSE DIAGRAM' shows~possible data transfer examples.In 3-wire-bus mode pin 11 becomes automatically the Locksignal output. An improved lock detect circuit generates a flag when the loop has attained lock. 'In lock' is indicated by a low impedance state (on) of the open collector output.In 3-wire-bus mode there is always the high charge pump current active. Only in IzC-bus mode the charge pump current can be controlled.