Features: • Complete single-chip channelized DS3 solution
• RISC processor with royalty-free DD-AMPS™ firmware (Drivers, Data link, Alarms, Messaging,
Performance/configuration objects, and Signaling)
• Host communication via royalty-free, messagebased, POSIX-compatible API
• Integrated 672 x 4,096-channel DS0 cross connect supports grooming, broadcast, off-bus hairpinning, and bonding
• Integrated DS1 cross connect
• 28 DS1 line interfaces or 1 DS3 line interface
• Combination of unframed DS1, transmission DS1, and either MVIP or H.100/H.110 as terminal side interfaces
• Selectable DS3 clear channel functionality
• On-chip maintenance of 15-minute performance objects per IETF RFCs 2495, 2496, and 2494.
• Two DS1 monitor ports for monitoring any DS1 clock and data
• Test Access Port (IEEE 1149.1 boundary scan)
• +3.3 volt input/output leads, +5 volt tolerant
• +3.3 volt and +1.8 volt power supplies
• 456-lead plastic ball grid array package (27 mm x 27 mm)Application• T-carrier termination equipment: muxes, inverse muxes, cross connects, groomers
• CT (Computer Telephony) network interface boards
• VoP (Voice over Packet/Cell) gateways
• MSADs (Multi-Service Access Devices)
• DSLAMs (Digital Subscriber Loop Access Multiplexers)
• ECUs (Echo Cancellation Units)Specifications
| Parameter |
Symbol |
Min |
Max |
Unit |
Conditions |
| Core Supply Voltage, +1.8V nominal |
VDD-INT |
-0.3 |
2.1 |
V |
Note 1,4 |
| I/O Supply Voltage, +3.3V nominal |
VDD-IO |
-0.3 |
3.9 |
|
Note 1,4 |
| DC input voltage |
VIN |
-0.5 |
5.5 |
V |
Note 1,4 |
| Storage temperature range |
TS |
-55 |
150 |
oC |
Note 1 |
| Ambient operating temperature |
TA |
-40 |
85 |
oC |
0 ft/min linear airflow.
Note 1 |
| Moisture Exposure Level |
ME |
5 |
|
Level |
per EIA/JEDEC
JESD22-A112-A |
| Relative humidity, during assembly |
RH |
30 |
60 |
% |
Note 2 |
| Relative humidity, in-circuit |
RH |
0 100 |
% |
non-condensing |
| ESD Classification |
ESD |
Absolute value 2000 |
V |
Note 3 |
| Latch-up |
LU |
|
|
|
Meets JEDEC STD-78 |
Notes:
1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability.
2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied.
3. Test method for ESD per MIL-STD-883D, Method 3015.7.
4. Device core is 1.8V only. All input signal leads accept 5V signals.
DescriptionT3BwP™ (TXC-06826) is a RISC processor-based device that supports the requirements of next-generation channelized DS3 access systems. T3BwP integrates an M13 multiplexer, 28 DS1 framers, and a 672 x 4,096-channel DS0 cross connect with an embedded high-performance microprocessor to provide a complete channelized DS3 solution on a single chip. The embedded processor firmware handles device drivers, data links, alarms, messaging, MIB performance objects, and signaling functions and allows communication to an external host via high-level API messages. The firmware is provided by TranSwitch and loaded from an external serial EEPROM at device boot-up.
The TXC-06826 can be configured to support a variety of modes of operation, which allows for design flexibility. TXC-06826 supports a combination of unframed DS1, transmission DS1 and H.100/H.110 bus or MVIP interfaces on the terminal side and either DS3 or DS1 on the line side. For TDM applications, all 672 DS0 channels can be switched to any of the 4,096 H.100/H.110 computer telephony (CT) bus channels. The TXC-06826 can also be enabled to provide DS3 C-bit parity for unchannelized services. The on-chip firmware provides the control and management plane functionality to the host to configure, control and monitor all DS3, DS1, DS0 and digital cross connect functions. The standardsbased
MIB functionality is provided for network management.
TXC-06826 Data Sheet
