TXC-02302B

• Transmits and receives at STS-3/STM-1 rates
• Compatible with available optical components
• Detects frame of incoming 155.52 Mbit/s signal, converts it to a 19.44 MByte/s or a 38.88 Mnib/s parallel signal, clock and frame on terminal side
• Receives 19.44 MByte/s or 38.88 Mnib/s data from terminal, converts to serial data on the line side
• Pseudo-ECL receive and transmit clock and data ports
• Provides loopback of clock and data in both directions
• Optionally performs scrambling/descrambling and B1 parity calculations
• Performance monitoring of the received signal includes:
   - Loss of Signal (LOS)
   - Out of Frame (OOF)
   - Loss of Frame (LOF)
   - Receive Frame Error (RFE)
• Compliant with ANSI and ITU-T (CCITT) documents:
   - ANSI T1.105-1991
   - ITU-T (CCITT) G.708
• Transmit and reference clock framing signal inversion capability

Notes:
1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability.
2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied.
3. Test method for ESD per MIL-STD-883D, Method 3015.7.

The SYN155C synchronizer device provides a complete STS-3/STM-1 frame synchronization function in a single low-power CMOS unit. The SYN155C performs the frame synchronization algorithm defined in ANSI/ITU-T (CCITT) publications on an incoming 155.52 Mbit/s signal, and outputs signal bytes or nibbles along with a byte/ nibble clock and frame indication signal. In the transmit direction, bytes or nibbles from a SONET/SDH device are accepted and sent out in serial to the fiber transmitter with a separate transmit clock signal.

The SYN155C supports two frame synchronization modes: a full tracking mode which finds frame and verifies it on following frames; and a non-tracking mode which finds frame but performs no verification.The serial line side is designed to connect directly to the fiber interface components using pseudo-ECL voltage levels (ECL operating from +5 V to ground), thus avoiding the need for ECL-to-TTL or ECL-to-CMOS level conversion.