TXC-02623

The TXC-02623 has the following features including Byte-parallel multiplexing, demultiplexing, framing, and clock synthesis PLL in one device;Choice of STS-12/STM-4 or STS-3/STM-1 transmission rates;Configurable master or slave reference clock generation by PLL, or bypass for external clock;Two versions of device to accommodate either of two reference clock input frequencies for the master clock: 51.84 MHz for the "A" version device or 38.88 MHz for the "B" version device;External RC loop filter;Pass-through mode and three loopback modes for enhanced field diagnostics Frame-synchronous and bytealigned demultiplexer output, according to SONET/SDH framing standards;Search, detect, and recovery of framing on out-of-frame (00F) input;Standard TTL and differential or single-ended ECL I/O (except TXCK is single-ended only);Tri-state TTL output for factory circuit-board test-ability.

The TXC-02623 STAF VLSI device is a SONETISDH transceiver and framer. It combines multiplexing, demultiplexing,SONET/SDH framing, clock synthesis PLL, and loop-back functions in a single monolithic integrated circuit.Implementation with the STAF device requires only a simple external RC loop filter and standard TTL and ECL power supplies. For optimal performance, the STAF device is packaged in a 68-pin multilayer ceramic (MLC) surface-mount package with an integral heat spreader. The STAF device provides physical interfaces for STS-12/STM-4 (622.08 Mbit/s)  or STS-3/ STM-1 (155.52 Mbit/s) SONET/SDH systems.

If TXC-02623 is desired to set the device into one of the eight temporary states, OH-7H, in which CNTL3=0, then CNTL3 should first be switched from 1 to 0. This will latch the current state of the clock rate and modes selection until CNTL3 is returned to 1 .When CNTL3 becomes 0 the device will enter the temporary state in Figure 8 defined by the CNTL(2-0) values last selected for clock rate and modes while CNTL3 was 1.If a different state is desired, the values of CNTL(2-0) should be changed accordingly to effect an immediate change. Any desired sequence of such temporary states may be selected in turn by changing CNTL(2-0) while holding CNTL3 at 0.When TXC-02623 is desired to return to normal operation, then CNTL(2-0) should be reset to the values for clock rate and modes selection that they had before CNTL3 was switched from 1 to 0. This will place the device into the corresponding temporary state once again.  CNTL3 should then be changed from 0 to 1 to restore normal operation without changing the clock rate and modes selection from their previous states.