TXC-06203

Notes:
1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or
Max values for extended periods may impair device reliability.
2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied.
3. Input signal leads can accept 5 volt signals from the outputs of 5 volt devices.
4. Absolute value tested per MIL-STD-883D, Method 3015.7.

The TranSwitch PHAST-3P (TXC-06203) is an STM-1/STS-3c section, line and path overhead termination device that
performs ATM and PPP PHY-layer processing. TXC-06203 provides either a SDH/SONET pseudo-ECL bit-serial interface or a bytewide parallel interface on the line side. The serial interface provides 155 MHz clock recovery and clock synthesis, and the section and line overhead bytes in the data are processed. The PHAST-3P performs pointer tracking and POH byte processing. TOH (RSOH and MSOH) and POH bytes are provided in RAM for microprocessor access or via TOH and POH interfaces. The POH bytes can be inserted from RAM, the serial POH interface, or a mate PHAST-3P device for line and path ring applications. The terminal interface is UTOPIA level 2 for ATM cells or level 2P for packets. UTOPIA bus width can be 8-bit or 16-bit, Single-PHYand Multi-PHY operation are supported.

For testing, the TXC-06203 provides boundary scan, B2 and B3 BER measurements, programmable BIP error mask generation, and line loopback. The  TXC-06203 device provides either Intel or Motorola microprocessor access. Performance counters can be configured to be saturating or roll-over. The interrupts, with mask bits, can be programmed for positive, negative, or positive/ negative alarm transitions or positive levels. A software polling register is also provided. A fully functional Device Driver is available through TranSwitch Applications Engineering.