Features: • Bit-serial, nibble-parallel, and byte-parallel interface capability, selectable via control bits• Transmit and receive clock rate: 100 Hz to 78 MHz for serial, nibble, byte I/O (all telecom rates up to OC-12/STM-4)• Test patterns at up to 622 Mbit/s using byteparallel...
TXC-06125: Features: • Bit-serial, nibble-parallel, and byte-parallel interface capability, selectable via control bits• Transmit and receive clock rate: 100 Hz to 78 MHz for serial, nibble, byte I...
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Features: • Transmits and receives at STS-3/STM-1 rates• Compatible with available opt...
Parameter | Symbol | Min* | Max* | Unit |
Supply voltage | VDD | -0.3 | 7.0 | V |
DC input voltage | VIN | -0.5 | VDD + 0.5 | V |
Continuous power dissipation | PC | ** | mW | |
Ambient operating temperature | TA | ** | ** | oC |
Operating junction temperature | TJ | 125 | oC | |
Storage temperature range | TS | -55 | 125 | oC |
*Operating conditions exceeding those listed in Absolute Maximum Ratings may cause permanent failure. Exposure to absolute maximum ratings for extended periods may impair device reliability.
**The minimum and maximum allowable ambient operating temperatures, and the maximum power dissipation, will be dependent on the total thermal analysis.
The Bit Error Rate Generator/Receiver (XBERT) VLSI device is a microprocessor-programmable multi-rate test pattern generator and receiver on a single chip. XBERT is used for testing the performance of digital communication circuits and communication links. It provides a bitserial, nibble-parallel or byte-parallel interface, and is capable of operating in a burst data mode by using external signals to enable/disable the transmit and receive clocks. The XBERT generates and analyzes pseudo-random patterns, fixed words, or programmable words. Four pseudo-random test patterns are provided: 215 - 1, 220 - 1, 220 - 1 with zero suppression (Quasi- Random Signal Source, not available in byte-parallel mode), and 223 - 1. The fixed word mode generates and analyzes all zeros, all ones, alternate one/zero pattern or a double alternate one/zero (1100) pattern. The programmable mode allows a choice of one to four bytes
written by the microprocessor.