TXC-03453

Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE  DH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal using a bytewide parallel interface in the TranSwitch Telecom Bus format. The TL3M supports Drop bus and Add bus SDH/SONET timing modes. Drop bus timing provides the timing signals for the add side. Timing for both buses is independent for the Add bus timing mode. Individual POH bytes are mapped into a RAM interface for microprocessor access and to an external interface for external processing if required. In the add direction (except for the B3 byte) POH bytes may be inserted individually from RAM locations, from the external interface, or from the local side/alarm indication port. An option is provided to generate an unequipped channel or AIS. An external interface is provided for accessing the O-bits. An alarm indication port is provided for ring operation. The TL3M also uses internal digital desynchronizers that have a built-in pointer leak algorithm. The line side can be configured for a NRZ or positive/negative rail interface. For testing purposes, the TL3M provides boundary scan, PRBS generators and analyzers, a BIP error mask, and DS3/E3 line and facility loopbacks. The TL3M provides either Motorola or Intel microprocessor access. The interrupt has programmable mask bits. A software polling register is also provided.