TXC-03452B

Notes:
1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability.
2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied.
3. VIN may not exceed the actual operating supply voltage (VDD) by more than 0.5 volt.
4. Test method for ESD per MIL-STD-883D, Method 3015.7.
5. This note applies to product TXC-03452CIOG only. AGND leads F13 and G4 have shown an ESD sensitivity at absolute levels of 1500 volts and above. APWR lead F16, APWR lead G1 and APWR2 lead G16 have shown an ESD sensitivity at absolute levels of 1500 volts and above.

The L3M maps a DS3 line signal into an STM-1 TUG-3 or STS-3/ STS-1 SPE or STS-1 SPE SDH/SONET signal. An E3 line signal is mapped into an STM-1 TUG-3 signal only. The L3M provides a TUG-3 formatted signal for STM-1 operation, or an STS SPE for STS-3 or STS-1 operation. The SDH/SONET signal is transmitted via an add bus with timing derived from the drop side, add side or from external timing (STS-1 only). An option is provided to generate the A1, A2 framing pattern, C1 byte and H1, H2 pointer towards the add bus when external timing mode is selected.

Individual POH bytes for the transmitted SDH/SONET signal are mapped from the L3M memory map or an external interface. An option is provided to generate an unequipped status or TUG-3 path AIS signal. External accesses are provided for the communications channel "O"-bits and alarms for ring operation. The received signal is desynchronized from drop bus STM-1/TUG-3, STS-3/STS-1 SPE, or STS-1 signals. Internal pointer processing is performed for the TUG-3 signal. All POH bytes are provided for the microprocessor.