Features: SpecificationsDescription The TXC-03351 has the following features including Reduces receive fitter on DS1 signals due to transmission and stuffing source fitter;Dejitters four DS1 signals Satisfies Bellcore category I fitter requirements for DS1 signals;Intertaces with DS1 line interta...
TXC-03351: Features: SpecificationsDescription The TXC-03351 has the following features including Reduces receive fitter on DS1 signals due to transmission and stuffing source fitter;Dejitters four DS1 signal...
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Features: • Transmits and receives at STS-3/STM-1 rates• Compatible with available opt...
The TXC-03351 has the following features including Reduces receive fitter on DS1 signals due to transmission and stuffing source fitter;Dejitters four DS1 signals Satisfies Bellcore category I fitter requirements for DS1 signals;Intertaces with DS1 line intertace devices;For use following a DS3 demux such as TranSwitch's M13 device;Designed with digital signal processing techniques.
The TXC-03351 Quad DS1 Dejitter Buffer (DJB) is one of a family of related DS3IDS1 products from TranSwitch. The TXC-03351 DJB performs fitter reduction on a DS1 signal when used in conjunction with a multiplexer (M13) device. Jitter occurs because the multiplexing process requires stuffing to compensate for differences in clock frequencies.In addition, noise, crosstalk, and clock recovery mechanisms in repeaters introduce timing fitter in DS1 signals.The DJB device uses a patented digital signal processing technique to reduce fitter caused by these sources.The DJB is used primarily with TranSwitch's M13 device to dejitter four DS1 signals. It is normally connected between the four DS1 multiplex outputs and their line interface devices.Operating conditions exceeding those listed in Absolute Maximum Ratings may cause permanent failure. Exposure to absolute maximum ratings for extended periods may impair device reliability.Figure 1 illustrates the block diagram of the DJB device. Each dejitter block contains a FIFO, programmable counters, and other digital logic circuits. The DS3 input clock (C44736) provides a clock source for deriving the clock for the DS1 outputs. The DJB uses a digital arithmetic unit to divide the input reference clock by a variable rate which depends on the state of the FIFO in each of the dejitterfunctional blocks.
TXC-03351 reserves the right to make changes to the product(s) or circuit(s) described herein with-out notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product or circuit.PRELIMINARY information documents contain information on products in the sampling or preproduction phase of development.Characteristic data and other specifications are subject to change.