Features: · Low power consumption: 230mW@40Msps·Single supply voltage: 2.5V Independent supply for CMOS output stage with 2.5V/3.3V capability·SFDR= -68.3 dBc @ Fin=10MHz· 1GHz analog bandwidth Track-and-Hold· Common clocking between channels·Dual simultaneous Sample and Hold inputs· Multiplexed o...
TSA1203: Features: · Low power consumption: 230mW@40Msps·Single supply voltage: 2.5V Independent supply for CMOS output stage with 2.5V/3.3V capability·SFDR= -68.3 dBc @ Fin=10MHz· 1GHz analog bandwidth Trac...
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Symbol |
Parameter |
Values |
Unit |
AVCC |
Analog Supply voltage 1) |
0 to 3.3 |
V |
DVCC |
Digital Supply voltage 1) |
0 to 3.3 |
V |
VCCBE |
Digital buffer Supply voltage 1) |
0 to 3.6 |
V |
VCCBI |
Digital buffer Supply voltage 1) |
0 to 3.3 |
V |
IDout |
Digital output current |
-100 to 100 |
mA |
Tstg |
Storage temperature |
+150 |
°C |
ESD |
HBM: Human Body Model2) CDM: Charged Device Model3) |
2 1.5 |
KV |
Latch-up | Class4) |
A |
The TSA1203 is a new generation of high speed, dual-channel Analog to Digital converter processed in a mainstream 0.25m CMOS technology yielding high performances and very low power consumption.
The TSA1203 is specifically designed for applications requiring very low noise floor, high SFDR and good isolation between channels. It is based on a pipeline structure and digital error correction to provide high static linearity at Fs=40Msps, and Fin=10MHz.
For each channel, a voltage reference is integrated to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references.
Each ADC outputs are multiplexed in a common bus with small number of pins. A tri-state capability is available for the outputs, allowing chip selection. The inputs of the ADC must be differentially
driven.
The TSA1203 is available in extended (0 to +85°C) temperature range, in a small 48 pins TQFP package.