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TSA1002

Features: · 10-bit A/D converter in deep submicron CMOS technology· Single supply voltage: 2.5V· Input range: 2Vpp differential· 50Msps sampling frequency· Ultra low power consumption: 50mW @ 50Msps· ENOB=9.4 @ Fs=50Msps, Fin=15MHz· SFDR typically up to 72dB @ Fs=50Msps, Fin=5MHz· Built-in referen...

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SeekIC No. : 004529069 Detail

TSA1002: Features: · 10-bit A/D converter in deep submicron CMOS technology· Single supply voltage: 2.5V· Input range: 2Vpp differential· 50Msps sampling frequency· Ultra low power consumption: 50mW @ 50Msps...

TSA1002 Data Sheet

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Part Number:
TSA1002
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· 10-bit A/D converter in deep submicron CMOS technology
· Single supply voltage: 2.5V
· Input range: 2Vpp differential
· 50Msps sampling frequency
· Ultra low power consumption: 50mW @ 50Msps
· ENOB=9.4 @ Fs=50Msps, Fin=15MHz
· SFDR typically up to 72dB @ Fs=50Msps, Fin=5MHz
· Built-in reference voltage with external bias capability
· STMicroelectronics 8, 10, 12 and 14-bits ADC pinout compatibility


Application

· Medical imaging and ultrasound
· Portable instrumentation
· Cable Modem Receivers
· High resolution fax and scanners
· High speed DSP interface


Pinout

Connection Diagram


Specifications

Symbol
 Parameter
Values
Unit
AVCC
 Analog Supply voltage 1)
0 to 3.3
V
DVCC
 Digital Supply voltage 1)
0 to 3.3
V
VCCB
 Digital buffer Supply voltage 1)
0 to 3.3
V
IDout
 Digital output current
-100 to 100
mA
Tstg
 Storage temperature
+150
°C
ESD
 Electrical Static Discharge
- HBM
- CDM-JEDEC Standard
2
1.5
KV
1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input
    and output voltages must never exceed -0.3V or VCC+0V


Description

The TSA1002 is a 10-bit, 50Msps sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1002 is based on a pipeline structure and digital error correction to provide excellent static linearity and guarantee 9.4 effective bits at
Fs=50Msps, and Fin=15MHz.

A voltage reference is integrated in the circuit to simplify the design and minimize external components. It is nevertheless possible to use the circuit with an external reference. Especially designed for high speed, low power applications, the TSA1002 only dissipates 50mW at 50Msps. A tri-state capability, available on the output buffers, enables to address several slave ADCs by a unique master.

The output data can be coded into two different formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes.

The TSA1002 is available in commercial (0 to +70°C) and extended (-40 to +85°C) temperature range, in a small 48 pins TQFP package.




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