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THC63LVDF84B

Features: • Wide VCC range: 2.5~3.6V• Wide dot clock range: 20-85MHz suited for VGA,SVGA, XGA and SXGA (VCC=3.0~3.6V)• Wide dot clock range: 20-70MHz suited for VGA,SVGA, XGA and SXGA (VCC=2.5V~3.6V)• PLL requires No external components• Rx power consumption < 80mW...

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SeekIC No. : 004518653 Detail

THC63LVDF84B: Features: • Wide VCC range: 2.5~3.6V• Wide dot clock range: 20-85MHz suited for VGA,SVGA, XGA and SXGA (VCC=3.0~3.6V)• Wide dot clock range: 20-70MHz suited for VGA,SVGA, XGA and S...

THC63LVDF84B Data Sheet

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Part Number:
THC63LVDF84B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Wide VCC range: 2.5~3.6V
• Wide dot clock range: 20-85MHz suited for VGA,SVGA, XGA and SXGA (VCC=3.0~3.6V)
• Wide dot clock range: 20-70MHz suited for VGA,SVGA, XGA and SXGA (VCC=2.5V~3.6V)
• PLL requires No external components
• Rx power consumption < 80mW @VCC 2.5V,65MHz Grayscale
• Power-Down Mode
• Low profile 56 Lead or 48 Lead TSSOP Package
• Pin compatible with THC63LVDF84A/F64A


Pinout

Connection Diagram


Specifications

Supply Voltage (Vcc).............................. -0.3 to +4V
CMOS/TTL Input Voltage ...........-0.3 to (Vcc + 0.3V)
CMOS/TTL Output Voltage...... -0.3V to (Vcc + 0.3V)
LVDS Receiver Input Voltage...-0.3V to (Vcc + 0.3V)
Junction Temperature.................................. +125
Storage Temperature Range............. -55 to +150
Resistance to soldering heat.............. +260 /10sec
Maximum Power Dissipation....................@25 0.5W


Description

The THC63LVDF84B/THC63LVDF64B receiver supports wide VCC range(2.5~3.6V). At single 2.5V supply, the THC63LVDF84B/THC63LVDF64B reduces EMI and power consumption.

The THC63LVDF84B receiver convert the four LVDS(Low Voltage Differential Signaling) data streams back into 28bits of CMOS/TTL data with falling edge clock.

At a transmit clock frequency of 85MHz, 28bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 2.3Gbps.

Also the THC63LVDF64B receiver convert the three LVDS data streams back into 21bits of CMOS/TTL data with falling edge clock.

At a transmit clock frequency of 85MHz, 21bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 1.78Gbps.




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