Features: ·21:3 Data channel compression at up to·223 Megabytes per sec throughput·Wide Frequency Range: 20 - 85 MHz·suited for VGA,SVGA,XGA and SXGA·Narrow bus (8 lines) reduces cable size·345mV swing LVDS devices for Low EMI·Supports Spread Spectrum Clock Generator·On chip Input Jitter Filtering...
THC63LVDF64A: Features: ·21:3 Data channel compression at up to·223 Megabytes per sec throughput·Wide Frequency Range: 20 - 85 MHz·suited for VGA,SVGA,XGA and SXGA·Narrow bus (8 lines) reduces cable size·345mV sw...
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Features: • Wide dot clock range: 8-135MHz suited for NTSC,VGA, SVGA, XGA,SXGA and SXGA+R...
Features: • Wide dot clock range: 8-90MHz suited for NTSC, VGA, SVGA, XGA, and WXGA• P...
Features: • Wide dot clock range: 8-112MHz suited for NTSC, VGA, SVGA, XGA, and SXGA• ...
Supply Voltage (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to +4V
CMOS/TTL Input Voltage . . . . . . . . . . . . . . . . .. . .-0.3V to (Vcc + 0.3V)
CMOS/TTL Output Voltage . . . . . . . . . . . . . . . . . . . -0.3V to (Vcc + 0.3V)
LVDS Receiver Input Voltage . . . . . . . . . . . . . . . . . -0.3V to (Vcc + 0.3V)
LVDS Driver Output Voltage . . . . . . . . . . . . . .. . . . -0.3V to (Vcc + 0.3V)
Output Short Circuit Duration continuous
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Lead Temperature(Soldering, 4 sec.) . . . . . . . . . . . . . . . . . . . .+260°C
Maximum Power Dissipation @25°C . . . . . . . . . . . . . . . . . . . . . . . 1.4W
Note 1:"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not ment to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
The THC63LVDM63A transmitter converts 21 bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. The THC63LVDM63A can be programmed for rising edge or falling edge clocks through a dedicated pin.
The THC63LVDF64A receiver convert the LVDS data streams back into 21 bits of CMOS/TTL data with falling edge clock. At a transmit clock frequency of 85MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (HSYNC, VSYNC, CNTL1) are transmitted at a rate of 595 Mbps per LVDS data channel.