Features: • Wide dot clock range: 25-135MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA• PLL requires No external components• Supports Dual Link, Dual-in (TTL)/Dual-out (LVDS) pixel up to 170MHz dot clock for UXGA• Supports Single Link, Dual-in (TTL)/Single-out (LVDS) p...
THC63LVD823: Features: • Wide dot clock range: 25-135MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA• PLL requires No external components• Supports Dual Link, Dual-in (TTL)/Dual-out (LVDS) ...
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Features: • Wide dot clock range: 8-135MHz suited for NTSC,VGA, SVGA, XGA,SXGA and SXGA+R...
Features: • Wide dot clock range: 8-90MHz suited for NTSC, VGA, SVGA, XGA, and WXGA• P...
Features: • Wide dot clock range: 8-112MHz suited for NTSC, VGA, SVGA, XGA, and SXGA• ...
• Wide dot clock range: 25-135MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
• PLL requires No external components
• Supports Dual Link, Dual-in (TTL)/Dual-out (LVDS) pixel up to 170MHz dot clock for UXGA
• Supports Single Link, Dual-in (TTL)/Single-out (LVDS) pixel up to 135MHz dot clock for SXGA+
• Supports Single Link, Single-in (TTL)/Single-out (LVDS) pixel up to 85MHz dot clock for XGA
• Clock edge selectable
• Supports Reduced swing LVDS for Low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 100pin TQFP
• THC63LVDM83R compatible
Supply Voltage (VCC) | -0.3V ~ +4.0V |
CMOS/TTL Input Voltage | -0.3V ~ (VCC + 0.3V) |
CMOS/TTL Output Voltage | -0.3V ~ (VCC + 0.3V) |
LVDS Receiver Input Voltage | -0.3V ~ (VCC + 0.3V) |
Output Current | -30mA ~ 30mA |
Junction Temperature | +125°C |
Storage Temperature Range | -55°C ~ +125°C |
Resistance to soldering heat | +260 °C |
Maximum Power Dissipation @+25 °C | 1.0W |
The THC63LVD823 transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. In Single Link, the transmit clock frequency of 135MHz, 48bits of RGB data are transmitted at an effective rate of 945Mbps per LVDS channel. Using a 135MHz clock, the data throughput is 472Mbytes per second.
In Dual Link, the transmit clock frequency of 85MHz, 48bits of RGB data are transmitted at an effective rate of 595Mbps per LVDS channel. Using a 85MHz clock, the data throughput is 595Mbytes per second.