TDA8960

· One-chip Advanced Television Systems Committee (ATSC)-compliant demodulator and concatenated trellis (Viterbi)/Reed Solomon decoder with de-interleaver and de-randomizer
· 0.4 mm process
· 3.3 V device
· 64-lead QFP64 package
· Boundary scan test
· Output format: 8-bit wide bus.

The TDA8960 is an ATSC-compliant demodulator and forward error correction decoder for reception of 8-VSB modulated signals for terrestrial and cable applications: ` Terrestrial: reception of 8-VSB modulated signals via standard 6 MHz VHF/UHF terrestrial TV channels (TV channels 2 to 69 in the United States) ` Cable: reception of 8-VSB modulated signals via standard 6 MHz VHF/UHF cable TV channels.

Most of the loop components of the TDA8960 needed to recover the data from the received symbols are internal. The only required external loop components are a low-speed serial D/A converter and a Voltage Controlled crystal Oscillator (VCXO) for the symbol timing recovery and an opamp integrator for the AGC. Loop parameters of the clock and carrier recovery can be controlled by the I²C-bus.

A tuner converts the incoming RF frequency to a fixed IF frequency centred at 44 MHz. The output of the tuner is filtered, followed by a down conversion in an IF block to a low IF frequency centred at 1/2 the VSB symbol rate (or a frequency of approximately 5.38 MHz). The low IF signal is applied to the A/D converter.

To use its full input span, the A/D converter is located within what is typically a fine AGC loop which includes a variable gain stage at the output of the IF block. However, it is also possible to apply the TDA8960 AGC control output directly to the tuner. The detector for the TDA8960 AGC output is located after the A/D converter and determines the peak level of the incoming signals. After gain control, the low IF signal is sampled at a nominal rate of twice the VSB symbol frequency, or approximately 21.5 MHz.

The carrier recovery is performed completely internally. This function consists of a digital frequency and Frequency Phase-Locked Loop (FPLL).

Data shaping is performed with a square root raised cosine (half Nyquist) filter with roll-off factor of 11.5%.

Symbol timing recovery is performed mostly within the TDA8960, except that a low cost D/A converter and VCXO are required externally to generate the nominal 21.52 MHz clock signal for the A/D converter and TDA8960.

After carrier recovery, half Nyquist filtering and symbol timing recovery, adaptive equalization is performed based on the use of the ATSC field sync (trained equalization) and/or the 8-VSB data itself (blind equalization). The adaptive equalizer uses a DFE structure.

After trellis decoding, the stream is de-interleaved with a convolutional de-interleaver (interleaving depth 52). The memory for de-interleaving is on-chip. The Reed Solomon decoder is ATSC-compliant with a length of 207 and can correct up to 10 bytes. The decoded stream is de-randomized using a Pseudo Random Bit Sequence (PRBS). Finally the data is passed to a First-In, First-Out (FIFO) register that prevents the appearance of irregular gaps in the output data.

The output of the TDA8960 is an ATSC-compliant MPEG-2 packet stream together with a clock. Furthermore some signal flags are provided to indicate the sync bytes and the valid data bytes. Uncorrected blocks are also indicated.

The 8-bit wide MPEG-2 stream can be applied to an MPEG-2 transport demultiplexer.