Features: · 8-bit resolution· Sampling rate up to 25 MHz· 30 MHz input signal bandwidth (full scale)· High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 25 MHz)· CMOS compatible digital inputs· External reference voltage ...
TDA8792: Features: · 8-bit resolution· Sampling rate up to 25 MHz· 30 MHz input signal bandwidth (full scale)· High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43...
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· 8-bit resolution
· Sampling rate up to 25 MHz
· 30 MHz input signal bandwidth (full scale)
· High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 25 MHz)
· CMOS compatible digital inputs
· External reference voltage regulator
· Power dissipation only 53 mW (typical)
· Standby mode (only 1.2 mW typical)
· Low analog input capacitance, no buffer amplifier required
· No sample-and-hold circuit required.
SYMBOL | PARAMETER | PARAMETER | MIN. | MAX. | UNIT |
VDDA | analog supply voltage | note 1 | -0.5 | +5.0 | V |
VDDD | digital supply voltage | note 1 | -0.5 | +5.0 | V |
VDDO | output stages supply voltage | note 1 | -0.5 | +5.0 | V |
VDD1 | supply voltage differences between VDD1 = VDDA - VDDD |
-0.5 | +5.0 | V | |
VDD2 | supply voltage differences between VDD2 = VDDD - VDDO |
-1.0 | +1.0 | V | |
VDD3 | supply voltage differences between VDD3 = VDDA - VDDO |
-1.0 | +1.0 | V | |
VI | input voltage | referenced to VSSA | -0.5 | +5.0 | V |
Vclk(p-p) | AC input voltage for switching (peak-to-peak value) |
referenced to VSSD | VDDD | V | |
IO | output current | 10 | mA | ||
Tstg | storage temperature | -50 | +150 | ||
Tamb | operating ambient temperature | -20 | +75 | ||
Tj | junction temperature | +125 |
The TDA8792 is a 8-bit analog-to-digital converter (ADC) for low-voltage, portable applications. It operates at 3.3 V and converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 25 MHz. The output data is valid after a delay of 6 clock cycles.