DescriptionThe TDA8771A is a triple 8-bit video Digital-to-Analog Converter (DAC). It converts the digital input signals into analog voltage outputs at a maximum conversion rate of 35 MHz. The device is fabricated in a 5 V CMOS process that ensures high functionality with low power dissipation. Th...
TDA8771A: DescriptionThe TDA8771A is a triple 8-bit video Digital-to-Analog Converter (DAC). It converts the digital input signals into analog voltage outputs at a maximum conversion rate of 35 MHz. The devic...
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The TDA8771A is a triple 8-bit video Digital-to-Analog Converter (DAC). It converts the digital input signals into analog voltage outputs at a maximum conversion rate of 35 MHz. The device is fabricated in a 5 V CMOS process that ensures high functionality with low power dissipation. The feature of TDA8771A are as follows: (1)8-bit resolution; (2)sampling rate up to: 35 MHz for TDA8772H/3, 85 MHz for TDA8772H/8; (3)internal reference voltage regulator; (4)no deglitching circuit required; (5)SYNC, BLANK control inputs; (6)3 independent clock inputs (one per DAC); (7)1 V output voltage range; (8)75 W output load; (9)TDA8772 has BLANK control on the 3 channels; (10)single 5 V power supply; (11)44-pin QFP package.
The absolute maximum ratings of the TDA8771A are: (1)analog supply voltage: -0.5V to +6.5V; (2)digital supply voltage: -0.5V to +6.5V; (3)supply voltage difference between VDDA and VDDD: -1.0V to +1.0V; (4)storage temperature: -55 to 150; (5)operating ambient temperature: 0 to +70; (6)junction temperature: +125.
The following is about the electrical characteristics of TDA8771A: (1)analog supply voltage: 4.5V min, 5.0V typical and 5.5V max; (2)digital supply voltage: 4.5V min, 5.0V typical and 5.5V max; (3)analog supply current: 10mA min, 33mA typical and 45mA max; (4)digital supply current: 7mA typical and 20mA max; (5)low level input voltage: 0V min and 1.2V max; (6)high level input voltage: 2.0V min and VDDD max; (7)input current: 0.6mA typical and 0.7mA max; (8)maximum clock frequency: 35MHz min; (9)clock pulse width high: 8ns min; (10)clock pulse width low: 8ns min; (11)input data set-up time: 4ns; (12)input data hold time: 4ns.