TDA8083

Features: ` One chip Digital Video Broadcasting (DVB) (ETS300421) compliant demodulator and concatenated Viterbi and Reed-Solomon decoder with de-interleaver and de-randomizer` 3.3 V supply voltage` Relevant outputs are 5 V tolerant to ease interface to 5 V environment` Few external components for...

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SeekIC No. : 004516670 Detail

TDA8083: Features: ` One chip Digital Video Broadcasting (DVB) (ETS300421) compliant demodulator and concatenated Viterbi and Reed-Solomon decoder with de-interleaver and de-randomizer` 3.3 V supply voltage`...

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Part Number:
TDA8083
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/12

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Product Details

Description



Features:

` One chip Digital Video Broadcasting (DVB) (ETS300421) compliant demodulator and concatenated Viterbi and Reed-Solomon decoder with de-interleaver and de-randomizer
` 3.3 V supply voltage
` Relevant outputs are 5 V tolerant to ease interface to 5 V environment
` Few external components for full application
` On-chip crystal oscillator (4 MHz) and Phase-Locked Loop (PLL) for internal clock generation
` Power-on reset module
` QPSK/BPSK demodulator:
   Different modulation schemes: Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK)
   Interpolator and internal anti-aliasing filter to handle variable symbol rates
   Tuner Automatic Gain Control (AGC) control
   Two on-chip matched 7-bit Analog-to-Digital Converters (ADCs)
   Square-root raised-cosine Nyquist
   Maximum symbol frequency of 30 Msymbols/s
   Can be used at low channel Signal-to-Noise Ratio (S/R)
   Internal full digital carrier recovery, clock recovery and AGC loops with programmable loop filters
   Two carrier recovery loops enabling optimum phase noise suppression
   S/R estimation.
` Viterbi decoder:
   Rate 1¤2 convolutional code based
   Constraint length K = 7 with G1 = 171oct and G2 = 133oct
   Supported puncturing code rates: 1¤2, 2¤3, 3¤4, 4¤5, 5¤6, 6¤7, 7¤8 and 8¤9
   4-bit 'soft decision' inputs for both I and Q
   Truncation length of 144
   Automatic synchronization to detect puncturing rate and spectral inversion
   Channel Bit Error Rate (BER) estimation from 10-2 to 10-8
   Differential decoding optional.
` Reed-Solomon (RS) decoder:
   (204, 188, T = 8) Reed-Solomon code
   Automatic synchronization of bytes, transport packets and frames
   Internal convolutional de-interleaving (I = 12; using internal memory)
   De-randomizer based on Pseudo Random Binary Sequence (PRBS)
   External indication of uncorrectable error (transport error indicator is set)
   Indication of the number of lost blocks
   Indication of the number of corrected blocks.
` Interface:
   I2C-bus interface initializes and monitors the demodulator and Forward Error Correction (FEC) decoder; a default mode is defined
   6-bit I/O expander for flexible access to and from the I2C-bus
   I2C-bus configurable interrupt input
   Switchable I2C-bus loop-through to suppress I2C-bus crosstalk in the tuner
   Digital Satellite Equipment Control (DiSEqC) 1.X, tone burst generation and tone mode with a 22 or 44 kHz carrier
   Parallel or serial output mode for MPEG transport stream (3-state mode also possible)
   Standby mode for reduced power consumption.
` Package: QFP100
` Boundary scan test.



Application

· Digital satellite TV: demodulation and FEC.


Description

This document specifies a DVB compliant demodulator and forward error correction decoder IC for reception of QPSK or BPSK modulated signals for satellite applications. The Satellite Demodulator and Decoder (SSD) can handle variable symbol rates without adapting the analog filters within the tuner. Typical applications for this device are:
· MCPC (Multi-Channel Per Carrier): one QPSK or BPSK modulated signal in a single satellite channel (transponder)
· Simul-cast: QPSK or BPSK modulated signal together with a Frequency Modulated (FM) signal in a single satellite channel (transponder).

The TDA8083 can handle variable symbol rates in the range of 12 to 30 Msymbols/s with a minimum number of low cost and non-critical external components.

The TDA8083 has minimal interfaces with the tuner. It only requires the demodulated analog I and Q baseband input signals and provides a tuner AGC control signal. Analog-to-digital conversion is done internally by two matched 7-bit ADCs.

The TDA8083 runs on a low frequency crystal which is upconverted to a clock frequency by means of an internal
PLL. Furthermore, the TDA8083 has an internal anti-alias filter, which can cover the range of symbol frequencies without the need to switch external (SAW) filters.

The TDA8083 has a double carrier loop configuration which has excellent capabilities of tracking phase noise.
Synchronization of the FEC unit is done completely internally, thereby minimizing I2C-bus communication.

The output of the TDA8083 allows different output modes (parallel or serial) to interface to a demultiplexer, descrambler or MPEG-2 decoder including a 3-state mode. For evaluation of the TDA8083, demodulator and Viterbi decoder outputs can be made available externally.

The SDD of the TDA8083 can be controlled and monitored by the I2C-bus. A 5-bit bidirectional I/O expander and an interrupt line are available. By sending an interrupt signal, the SDD can inform the microcontroller of its internal status. Separate resets are available for logic only, logic plus the I2C-bus and carrier loops. A switchable I2C-bus loop-through to the tuner is implemented to switch off the I2C-bus connection to the tuner. This reduces phase noise in the tuner in case of I2C-bus crosstalk. Furthermore, for dish control applications hardware supports DiSEqC 1.X and tone burst generation via I2C-bus control. A 22 or a 44 kHz carrier can be generated (tone mode).




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