TDA8050A

Features: · Programmable gain· PLL controlled carrier frequency· 3-wire transmission bus· 5 V supply voltage.Application· QPSK modulation.PinoutSpecifications SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage -0.3 +6.0 V tsc short-circuit time (every pin to...

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SeekIC No. : 004516666 Detail

TDA8050A: Features: · Programmable gain· PLL controlled carrier frequency· 3-wire transmission bus· 5 V supply voltage.Application· QPSK modulation.PinoutSpecifications SYMBOL PARAMETER MIN. M...

floor Price/Ceiling Price

Part Number:
TDA8050A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/12

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Product Details

Description



Features:

· Programmable gain
· PLL controlled carrier frequency
· 3-wire transmission bus
· 5 V supply voltage.




Application

· QPSK modulation.


Pinout

  Connection Diagram


Specifications

SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCC
supply voltage
-0.3
+6.0
V
tsc
short-circuit time (every pin to VCC or GND)
-
10
S
VMAX
voltage on all pins except BUF_OUT, BUF_OUTC and TUNE_CONV
-0.3
VCC
V
V(tune)
output tuning voltage
-0.3
+30
V
VO(buf)
output buffer voltage on pins BUF_OUTand BUF_OUTC
-
10
V
Ptot
maximum power dissipation
-
940
mW
Tamb
Operating ambient temperature
0
70
Tstg
storage temperature
-40
+150
Tj(max)
maximum junction temperature
-
150




Description

The Quadrature Phase Shift Keying (QPSK) transmitter TDA8050A is a monolithic bipolar IC dedicated to quadrature modulation of the I and Q signals. It includes:
   · Two double balanced mixers
   · A balanced voltage controlled oscillator (VCO) with 0 to 90 degrees signal generation for modulation
   · A phase locked loop (PLL) for IF frequency control
   · A conversion mixer
   · A PLL for RF frequency control
   · A gain controlled output amplifier
   · A 3-wire bus and an output buffer.

Two PLLs are incorporated, the first PLL includes:
   · A fixed main divider
   · A crystal oscillator and its programmable reference divider
   · A phase/frequency detector, combined with a fixed charge pump.

The second PLL includes:
   · A divide-by-four preamplifier
   · A 12-bit programmable divider
   · A crystal oscillator and its programmable reference divider
   · A phase/frequency detector, combined with a programmable charge pump which drives the tuning 
       amplifier,  including 30 V output.


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