Features: • Industry-standard x 16 pinouts and timing functions.• Single 5V (±10%) power supply.• All device pins are TTL- compatible.• 1K-cycle refresh in 16ms.• Refresh modes:RAS only,CAS BEFORERAS (CBR) and HIDDEN.• BYTE WRITE and BYTE READ access cycles.Pino...
T2316160A: Features: • Industry-standard x 16 pinouts and timing functions.• Single 5V (±10%) power supply.• All device pins are TTL- compatible.• 1K-cycle refresh in 16ms.• Refre...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
• Industry-standard x 16 pinouts and timing functions.
• Single 5V (±10%) power supply.
• All device pins are TTL- compatible.
• 1K-cycle refresh in 16ms.
• Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN.
• BYTE WRITE and BYTE READ access cycles.
Voltage on Any pin Relative to VSS.................... -1V to +7V
Operating Temperature, Ta (ambient)........ 0°C to +70°C
Storage Temperature (plastic)............... -55°C to +150°C
Power Dissipation ....................................................... 1.2W
Short Circuit Output Current........................................ 50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The T2316160A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x16 configuration. The T2316160A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode with Extended Data Output.
The T2316160A CAS function and timing of T2316160A are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL to transition low in a WRITE cycle will write data into the lower byte (DQ0~DQ7), and CASH transiting low will write data into the upper byte (DQ8~DQ15).