QS5935

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The QS5935 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Five outputs are available: Q0Q4. Careful layout and design ensure <500ps skew between the Q0Q4. The QS5935 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5935 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5935 clock driver represents the best value in small form factor, high-performance clock management products.