PLL650-07

Features:

• Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• 2 outputs fixed at 50MHz, 2 outputs fixed at 25MHz .
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 14-Pin 150mil SOIC.


Pinout




Specifications

PARAMETERS	SYMBOL	MIN.	MAX.	UNITS
Supply Voltage	VDD		4.6	V
Input Voltage, dc	VI	-0.5	VDD+0.5	V
Output Voltage, dc	VO	-0.5	VDD+0.5	V
Storage Temperature	TS	-65	150	°C
Ambient Operating Temperature*	TA	-40	85	°C
Junction Temperature	TJ		125	°C
Lead Temperature (soldering, 10s)			260	°C
ESD Protection, Human Body Model			2	kV

Description

The PLL650-07 is a low cost, low jitter, high performance clock synthesizer. With PhaseLink's proprietary analog Phase Locked Loop techniques, this device can produce multiple clock outputs from a 25.0MHz crystal or reference clock. This makes the PLL650-07 an excellent choice for systems requiring clocking for network chips and ASICs.