PCK2057

The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN,FBIN ), the 2-line serial interface (SDA, SCL), and the analog power input (AVDD). The two-line serial interface (I2C) of PCK2057 can put the individual output clock pairs in a high-impedance state. When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The PCK2057 provides a standard mode (100 kbits) I2C interface for device control. The implementation is as a slave/receiver. The serial inputs (SDA, SCL) provide integrated pull-up resistors (typically 100 kW).

Two 8-bit, 2-line serial registers of PCK2057 provide individual enable control for each output pair. All outputs default to enabled at power-up. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers is not supported). The I2C interface circuit of PCK2057 can be supplied with either 2.5 V or 3.3 V (VDDI2C).

Since the PCK2057 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power-up.