Features: • 3.3 V operation• Eight differential CPU clock pairs• One IO clock at 33 MHz and 66 MHz• Two 48 MHz clocks at 3.3 V• One 14.318 MHz reference clock• Power management control pins• Host clock jitter less than 200 ps cycle-to-cycle• Host clo...
PCK2022R: Features: • 3.3 V operation• Eight differential CPU clock pairs• One IO clock at 33 MHz and 66 MHz• Two 48 MHz clocks at 3.3 V• One 14.318 MHz reference clock• Po...
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SYMBOL |
PARAMETER |
CONDITION |
LIMITS
|
UNIT
| |
MIN |
MAX | ||||
VDD3 |
DC 3.3 V supply |
0.5 |
+4.6 |
V | |
IIK |
DC input diode current |
VI < 0 |
-50 |
mA | |
VI |
DC input voltage |
Note 2 |
0.5 |
VDD |
V |
IOK |
DC output diode current |
VO > VDD or VO < 0 |
±50 |
mA | |
VO |
DC output voltage |
Note 2 |
-0.5 |
VDD + 0.5 |
V |
IO |
DC output source or sink current |
VO >= 0 to VDD |
- |
±50 |
mA |
TSTG |
Storage temperature range |
65 |
+150 |
°C | |
Ptot |
Power dissipation per package plastic medium-shrink SO (SSOP) |
For temperature range: 0 to +70°Cabove +55°C derate linearly with 11.3mW/K |
- |
850 |
mW |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The PCK2022R is a clock synthesizer/driver for a Pentium IIIE and other similar processors
The PCK2022R has eight differential pair CPU current source outputs, one 33/66 MHz output which is configurable on power-up, two 48 MHz clocks which can be disabled on power-up, and one 3.3 V reference clock at 14.318 MHz which can also be disabled on power-up. All clock outputs meet Intel's drive strength, rise/fall times, jitter, accuracy, and skew requirements.
The part possesses a dedicated power-down input pin for power management control. This input is synchronized on chip, and ensures glitch-free output transitions. In addition, the part of PCK2022R can be configured to disable the 48 MHz outputs for lower power operation and an increase in the performance of the functioning outputs. The IOCLK and REFCLK of PCK2022R can also be disabled for the highest performance of the Host outputs.