Features: • ESD classification testing is done to JEDEC Standard JESD22. rotection exceeds 2000 V to HBM per method A114.• Latch-up testing is done to JEDEC Standard JESD78 hich exceeds 100 mA.• Mixed 2.5 V and 3.3 V operation• Six CPU clocks at 2.5 V• Six PCI clocks ...
PCK2014A: Features: • ESD classification testing is done to JEDEC Standard JESD22. rotection exceeds 2000 V to HBM per method A114.• Latch-up testing is done to JEDEC Standard JESD78 hich exceeds ...
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SYMBOL |
PARAMETER |
CONDITION |
LIMITS
|
UNIT
| |
MIN |
MAX | ||||
VDD3 |
DC 3.3 V core supply voltage |
0.5 |
+4.6 |
V | |
VDDQ3 |
DC 3.3 V I/O supply voltage |
0.5 |
+4.6 |
V | |
VDDQ2 |
DC 2.5 V I/O supply voltage |
0.5 |
+3.6 |
V | |
IIK |
DC input diode current |
VI < 0 |
-50 |
mA | |
VI |
DC input voltage |
Note 2 |
0.5 |
+5.5 |
V |
IOK |
DC output diode current |
VO > VCC or VO < 0 |
±50 |
mA | |
VO |
DC output voltage |
Note 2 |
-0.5 |
VCC + 0.5 |
V |
IO |
DC output source or sink current |
VO >= 0 to VCC |
- |
±50 |
mA |
TSTG |
Storage temperature range |
65 |
+150 |
°C | |
Ptot |
Power dissipation per package plastic medium-shrink SO (SSOP) |
For temperature range: 0 to +70°Cabove +55°C derate linearly with 11.3mW/K |
- |
850 |
mW |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The PCK2014A is a clock generator (frequency synthesizer) chip for Pentium III and other similar processors.
The PCK2014A has six CPU clock outputs at 2.5 V, two 3V66 clocks unning at 66 MHz. there are six PCI clock outputs running at33 MHz. Additionally, the part has three 2.5 V IOAPIC clock outputsat 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz.All clock outputs meet Intel's drive strength, rise/fall time, jitter,accuracy, and skew requirements.
The part possesses of PCK2014A dedicated power-down, CPUSTOP, andPCISTOP input pins for power management control. These inputsare synchronized on-chip and ensure glitch-free output transitions.When the CPUSTOP input is asserted, the CPU clock outputs and3V66 clock outputs are driven LOW. When the PCISTOP input isasserted, the PCI clock outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internalreference oscillator and PLLs PCK2014A are shut down, and all outputs aredriven LOW.