P4C174

Features: FEATURESHigh Speed Address-To-Match - 8 ns MaximumAccess TimeHigh-Speed Read-Access Time 8/10/12/15/20/25 ns (Commercial) 15/20/25 ns (Military)Open Drain MATCH OutputReset Function8-Bit Tag Comparison LogicAutomatic Powerdown During Long CyclesData Retention at 2V for Battery BackupOper...

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P4C174 Picture
SeekIC No. : 004439282 Detail

P4C174: Features: FEATURESHigh Speed Address-To-Match - 8 ns MaximumAccess TimeHigh-Speed Read-Access Time 8/10/12/15/20/25 ns (Commercial) 15/20/25 ns (Military)Open Drain MATCH OutputReset Function8-Bit T...

floor Price/Ceiling Price

Part Number:
P4C174
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

FEATURES
High Speed Address-To-Match - 8 ns Maximum
Access Time
High-Speed Read-Access Time
8/10/12/15/20/25 ns (Commercial)
15/20/25 ns (Military)
Open Drain MATCH Output
Reset Function
8-Bit Tag Comparison Logic
Automatic Powerdown During Long Cycles
Data Retention at 2V for Battery Backup
Operation
Advanced CMOS Technology
Low Power Operation
Package Styles Available
- 28 Pin 300 mil DIP
- 28 Pin 300 mil Plastic SOJ
Single Power S





Pinout

  Connection Diagram




Specifications

Symbol Parameter Value Unit
VCC Power Supply Pin with Respect to GND 0.5 to +7 V
VTERM Terminal Voltage with Respect to GND (up to 7.0V) 0.5 to VCC +0.5 V
TA Operating Temperature 55 to +125 °C





Description

The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible.

The cache tag RAMs P4C174 operate from a single 5V±10% power supply. An 8-bit data comparator with a MATCH output is included for use as an address tag comparator in high speed cache applications. The reset functionprovides the capability to reset all memory locations to a LOW level.

The MATCH output of the P4C174 reflects the comparison result between the 8-bit data on the I/O pins and the addressed memory location. 8K Cache lines can be mapped into 1M-Byte address spaces by comparing 20 address bits organized as 13-line address bits and 7- page address bits.

Low power operation of the P4C174 is enhanced by automatic powerdown when the memory is deselected or during long cycle times. Also, data retention is maintained down to VCC = 2.0. P4C174 battery backup applications consume only 30 W at VCC = 3.0V.






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