Features: `VCC Current (Commercial/Industrial)- Operating: 70mA/85mA- CMOS Standby: 100A/100A`Access Times-55/70 (Commercial or Industrial)`Single 5 Volts ±10% Power Supply`Easy Memory Expansion Using CE1, CE2 and OE Inputs`Common Data I/O`Three-State Outputs`Fully TTL Compatible Inputs and Output...
P4C1024L: Features: `VCC Current (Commercial/Industrial)- Operating: 70mA/85mA- CMOS Standby: 100A/100A`Access Times-55/70 (Commercial or Industrial)`Single 5 Volts ±10% Power Supply`Easy Memory Expansion Usi...
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Symbol | Parameter |
Min |
Max |
Unit |
VCC | Supply Voltage with Respect to GND |
-0.5 |
7.0 |
V |
VTERM | Terminal Voltage with Respect to GND (up to 7.0V) |
-0.5 |
VCC+0.5 |
V |
TA | Operating Ambient Temperature |
-55 |
125 |
|
STG | Storage Temperature |
-65 |
150 |
|
LOUT | Output Current into Low Outputs |
25 |
mA | |
ILAT | Latch-up Current |
>200 |
mA |
The P4C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM P4C1024L operates from a single 5V±10% tolerance power supply.
Access times of 55 ns and 70 ns are availale. CMOS P4C1024L is utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins of P4C1024L stay in the HIGH Z state when either CE1 orOE is HIGH orWE or CE2 is LOW.
The P4C1024L is packaged in a 32-pin 445 mil SOP as well as a 600 mil PDIP.